Abstract: Electric field communication that adopts a metal as a communication medium is performed. An electric field communication system communicating through an electric field, includes: a communication medium made of a material capable of transmitting the electric field; a first transmitter that generates an electric field dependent on a potential difference between a first electrode, which is disposed on a side of the communication medium and is connected to the communication medium via a coupling capacitance, and a second electrode connected to an earth ground via a coupling capacitance, with the first electrode being connected on a signal side of the transmitter, and the second electrode being connected on a ground side of the transmitter; and a first receiver disposed in contact with the communication medium, wherein the first transmitter and the first receiver communicate with each other through the electric field via the communication medium.

Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.

Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.

Abstract: A motor controlling circuit is provided. A first terminal of a first high-side transistor and a first terminal of a second high-side transistor are coupled to a common voltage. A first terminal of a first low-side transistor is connected to a second terminal of the first high-side transistor. A first node between the first terminal of the first low-side transistor and the second terminal of the first high-side transistor is connected to a first terminal of a motor. A first terminal of a second low-side transistor is connected to a second terminal of the second high-side transistor. A second node between the first terminal of the second low-side transistor and the second terminal of the second high-side transistor is connected to a second terminal of the motor. The driver circuit regulates at least one of the transistors such that no current flows to the common voltage.

Abstract: The data processing apparatus includes a memory protection setting storage unit capable of storing a plurality of address sections as memory protection setting targets, a plurality of first determination units provided for each of the address sections stored in the memory protection setting storage unit and provisionally determining whether or not an access request is permitted based on whether or not an access destination address specified by the access request corresponds to the address section acquired from the memory protection setting storage unit, and a second determination unit finally determining whether or not the access request is permitted based on the classification information and the results of provisional determinations by the first determination unit.

Abstract: A semiconductor device includes: a nonvolatile memory cell including first memory cells and second memory cells; a bit latch; and a saved register. In a first writing operation, first writing data are stored in the bit latch and the saved register, and writing to the first memory cells is executed based on the first writing data. During the first writing operation, the first writing operation is interrupted based on a suspension command, and a second writing operation is executed. In the second writing operation, second writing data are stored in the bit latch, and writing to the second memory cells is executed based on the second writing data. After the second writing operation is ended, the first writing data is reset to the bit latch based on a resume command, and the interrupted first writing operation is restarted based on the first writing data reset to the bit latch.

Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.

Abstract: A power converter having a smooth transition control mechanism is provided. An oscillator circuit outputs a clock signal. A control circuit receives the clock signal from the oscillator circuit and outputs a control signal based on the clock signal. A driver circuit outputs a high-side conduction signal and a low-side conduction signal according to the control signal. A high-side switch is turned on or off according to the high-side conduction signal from the driver circuit. A low-side switch is turned on or off according to the low-side conduction signal from the driver circuit. The oscillator circuit receives the high-side conduction signal from the driver circuit. The oscillator circuit, according to the high-side conduction signal, determines whether or not the clock signal outputted to the control circuit needs to be adjusted.

Abstract: Ensuring that a control program of a programmable electronic component included in an optical module updatable as well while a control program of a microprocessor included in the optical module is in operation. A module that functions by causing an electronic component to operate, a microprocessor located in the module and coupled to a host device via communicating device uses data in the S-record format downloaded from the host device using the communicating device to update a control program of the electronic component.

Abstract: An automatic control system for a phase angle of a motor is provided. A current detector circuit detects a current signal of the motor to output a current detected signal. A control circuit outputs a control signal according to the current detected signal indicating a time point at which the current signal reaches a zero value. A driver circuit outputs a driving signal according to the control signal. An output circuit operates to output a motor rotation adjusting signal to the motor to adjust a rotational state of the motor according to the driving signal.

Abstract: A torque sensor is capable of accurately attaching a first structure to an arm. A first structure includes a first surface, a second surface parallel to the first surface, and a third surface and a fourth surface connecting the first surface with the second surface. A second structure is concentrically arranged inside the first structure. A plurality of third structures connect the first structure with the second structure. The first structure comprises a plurality of protrusions on a part of the third surface. Each of the plurality of protrusions includes an inclined part becoming higher in a direction from the first surface to the second surface and a contact part continuous from a vertex of the inclined part, parallel to the third surface, and in a liner shape.

Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

Abstract: A method for Serial Peripheral Interface (SPI) operating-mode synchronization between an SPI host and an SPI device, which communicate over an SPI bus, includes predefining, in the SPI device, one or more values on the SPI bus as indicative of lack of synchronization of an SPI operating mode between the SPI host and the SPI device. Re-synchronization of the SPI operating mode is initiated in response to receiving any of the predefined values in the SPI device.

Abstract: A semiconductor device includes an operation resource which performs a plurality of ECU functions, a peripheral resource which is shared by the plurality of ECU functions and a control mechanism which controls a period in which one of the ECU functions uses the peripheral resource. The control mechanism calculates, based on a budget value which is given in advance and is a performance allocation, a use prohibition period in which the one of the ECU functions is prohibited from using the peripheral resource within the predetermined unit time.

Abstract: A semiconductor device of the present invention includes: a P-type output transistor configured to have a source to which a power supply voltage is applied, and a drain connected to an external connection pad; a gate wiring configured to be connected to a gate of the output transistor; a signal transmitting portion configured to transmit an input signal to the gate wiring; and a voltage-breakdown protecting portion configured to apply the power supply voltage to a back gate of the output transistor if a voltage on the external connection pad is equal to or lower than the power supply voltage, or the voltage-breakdown protecting portion bringing the signal transmitting portion into a disconnection state and applies the voltage on the external connection pad to the gate and the back gate of the output transistor if the voltage applied on the external connection pad is higher than the power supply voltage.

Abstract: A power converter having a mechanism of dynamically controlling a minimum off time is provided. A high-side overcurrent protecting circuit determines whether or not a current flows from a high-side switch through a node between a second terminal of the high-side switch and a first terminal of a low-side switch toward an inductor, and determines whether or not the current is larger than a threshold to output a high-side overcurrent detected signal and a high-side overcurrent protecting signal. An off time adjusting circuit outputs a minimum off time signal to a driver circuit according to the high-side overcurrent protecting signal. The driver circuit determines that an overcurrent event occurs when the high-side switch is turned on according to the high-side overcurrent detected signal, and accordingly the driver circuit at least continually turns on the low-side switch during a longer minimum off time of the minimum off time signal.

Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.

Abstract: An electronic component includes a pair of first engaging parts and a pair of second engaging parts. Both of the pair of first engaging parts are arranged at side surfaces of a case parallel to each other in opposition to each other. Each of the pair of second engaging parts is arranged adjacent to each of the pair of first engaging parts. Each of the first engaging parts includes a first arm and first protrusion, each of the second engaging parts includes a second arm and second protrusion, and a length of the second protrusion is longer than a length of the first protrusion.

Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.

Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.