Patents Assigned to ELECTRONICS CORPORATION
  • Patent number: 12080591
    Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: September 3, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Omori, Seiji Muranaka, Kazuyoshi Maekawa
  • Patent number: 12078540
    Abstract: An optical sensor having a common light sensing circuit for synchronously sensing a plurality of color light signals is provided. A plurality of photoelectric components respectively convert the plurality of color light signals into a plurality of photocurrents. A plurality of gain amplifiers respectively multiply the plurality of photocurrents by a plurality of gains to output a plurality of amplified photocurrents. An arithmetic circuit adds up the plurality of amplified photocurrents to output a total amplified photocurrent signal. A common analog-to-digital converter converts the total amplified photocurrent signal into a digital signal. A counter circuit counts bit values of the digital signal to output a counting signal.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: September 3, 2024
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Jia-Hua Hong
  • Patent number: 12078659
    Abstract: A semiconductor device includes a temperature sensor circuit having a sensor element, internal circuits, sensor terminals connected to the sensor element, and normal terminals connected to the internal circuits. A semiconductor inspection apparatus inspects, by using a probe card having first probes and second probes, the semiconductor device mounted on a stage in a first state in which the first probe is in contact with the sensor terminal and the second probe is not in contact with the semiconductor device and in a second state in which the first probe is in contact with the sensor terminal and the second probe is in contact with the normal terminal. The semiconductor inspection apparatus measures an output value of the sensor element in the first state to calculate temperature characteristics of the sensor element, and grasps a temperature of the sensor element in the second state based on the temperature characteristics.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: September 3, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masaaki Tanimura
  • Patent number: 12073900
    Abstract: A semiconductor device includes memory cells, word lines, a row address decoder, word line drivers, a first switch transistor, and second switch transistors. The switch transistor is provided between the word line drivers and a power supply potential terminal. Each second switch transistor is provided between each word line and a reference potential terminal. The row address decoder activates all of decode signals corresponding to the memory cells to which a burn-in test is performed collectively. The first switch transistor has a lower driving capability than a total driving capability of two P-channel MOS transistors included in inverters of two word line drivers. Each second switch transistor has a lower driving capability than a driving capability of an N-channel MOS transistor included in the inverter of each word line driver.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: August 27, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Haruyuki Okuda
  • Patent number: 12074357
    Abstract: An electromagnetic wave transmission board proofed against internal signal leakage includes an inner plate, a first outer plate, a second outer plate, a first plate bump, a first conductive bump, a second plate bump, and a second conductive bump. The inner plate defines a first through hole with a plated metal layer on the hole wall. The first and second plated bumps are disposed between the first outer and inner plates. The second plate bump and the second conductive bump are disposed between the second outer plate and the inner plate. The plate metal layer, the first plate bump, the first conductive bump, the first outer plate, the second outer plate, the second conductive bump, and the second plated bump jointly form an air-filled chamber. A method for manufacturing the electromagnetic wave transmission board is also provided.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: August 27, 2024
    Assignee: BOARDTEK ELECTRONICS CORPORATION
    Inventor: Chung-Hsing Liao
  • Patent number: 12068689
    Abstract: A power converter device is provided. A feedback circuit outputs a comparison output signal. A phase-locked loop circuit provides a phase-locked signal according to a reference clock signal and an inductor voltage in a power converter circuit. An on-time circuit provides an on-time comparing signal according to the phase-locked signal, an input voltage, the inductor voltage and an output voltage of the power converter circuit. A first input terminal of an SR flip-flop receives the on-time comparing signal from the on-time circuit. A second input terminal of the SR flip-flop receives the comparison output signal from the feedback circuit. A frequency control circuit, according to changes in the input voltage and the output voltage of the power converter circuit, instantaneously adjusts the on-time of the on-time signal such that an output terminal of the SR flip-flop outputs the adjusted on-time signal to the power converter circuit.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: August 20, 2024
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Jen-Chien Hsieh, Tsung-Yu Wu
  • Patent number: 12068421
    Abstract: A light shielding structure of an optical circuit of the present invention uses a part of the structure of the light reception element itself to suppress stray light. A stepped electrode that covers an upper surface and side surface of a first semiconductor layer constituting a light absorption portion of the light reception element is formed at a height substantially equal to that of an optical waveguide in the optical circuit, and the light absorption portion of the light reception element is shielded from stray light by a wall-shaped or column-shaped wiring electrode extending substantially perpendicularly to a surface layer of the optical circuit. The light shielding structure of the present invention uses a part of the configuration of the light reception element, is formed integrally with the light reception element, and also has an aspect of the invention of the light reception element.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 20, 2024
    Assignees: NTT ELECTRONICS CORPORATION, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Keiichi Morita, Atsushi Murasawa, Hiroki Kawashiri, Yusuke Nasu
  • Patent number: 12062627
    Abstract: A part among a plurality of through vias formed in a non-transistor region is a floating via having a floating potential.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 13, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshihiro Ohara
  • Patent number: 12061123
    Abstract: A semiconductor device includes a semiconductor substrate on which a temperature sensor is formed, a plurality of insulating films formed above the semiconductor substrate, a temperature measurement wiring pattern formed on a first insulating film which is one of the plurality of the insulating films, a detection electrode which is formed on the uppermost insulating film of the plurality of the insulating films to be arranged at a position corresponding to the first temperature measurement wiring pattern and is provided for contact a temperature measurement needle, and one or more via electrodes formed in one or more insulating film between the temperature measurement electrode and the detection electrode to couple between the temperature measurement electrode and the detection electrode.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: August 13, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shin Tamura, Shinji Kawashima, Hisao Kobashi
  • Patent number: 12061355
    Abstract: The frame assembly has a first direction and comprises a first frame, which has at least one exhausting passage, an adhesive layer, which has at least one through hole, and a second frame, which is connected to the first frame via the adhesive layer. A containing space is defined by the first frame and the second frame together and extends along the first direction. The exhausting passage fluidly communicates with the containing space and the external environment. The adhesive layer is disposed inside the containing space to divide the containing space into two venting passages that fluidly communicate with each other through the through hole. Residue air in the containing space is evacuated through the exhausting passage, increasing an adhered area and adhesion completeness of the adhesive layer, thereby increasing an adhesion-bonding strength of the two frames and structural stability of the frame assembly.
    Type: Grant
    Filed: December 29, 2023
    Date of Patent: August 13, 2024
    Assignee: RADIANT OPTO-ELECTRONICS CORPORATION
    Inventors: Chang-Ching Yen, Cheng-Te Chang, Pei-Fen Hou
  • Patent number: 12050921
    Abstract: A semiconductor device includes a processor unit, a memory storing a boot program, a reset controller and an address check unit. The reset controller controls a reset for the processor unit based on a reset request and outputs a boot address for the boot program to be executed after reset release to the processor unit. The address check unit performs a tampering check for the boot address output from the reset controller and outputs a boot address error signal based on a tampering check result.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: July 30, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Mori, Yuji Kubo, Hiroshi Morita
  • Patent number: 12047021
    Abstract: A motor driver having a high success rate starting mechanism is provided. A multi-segment slope pattern circuit connects a plurality of values of waveforms of a starting waveform signal to form a curve. The multi-segment slope pattern circuit determines a plurality of slopes respectively of a plurality of curve segments included in the curve according to a plurality of parameters related to a motor. The multi-segment slope pattern circuit outputs a multi-segment slope pattern signal according to the plurality of slopes of the plurality of curve segments. A startup signal generating circuit outputs a first startup waveform signal according to the multi-segment slope pattern signal. A motor controller circuit controls a motor driving circuit to start up the motor according to the first startup waveform signal.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: July 23, 2024
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Ming-Jung Tsai
  • Patent number: 12047023
    Abstract: A torque map generation system includes a motor, an inverter that drives the motor, a controller that controls the inverter, a torque sensor coupled to the motor, a power analyzer coupled to the torque sensor and a torque map generator that measures a current vector value of the motor by switching a MTPA (Maximum Torque Per Ampere) method and a square wave method based on a voltage utilization ratio of the inverter, wherein the torque map generator utilizes a measurement result by the MTPA method when the torque map generator uses the square wave method.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: July 23, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Chengzhe Li
  • Patent number: 12046318
    Abstract: A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: July 23, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuo Aita, Daisuke Kawakami, Toshiyuki Hiraki
  • Patent number: 12040399
    Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: July 16, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Tsukuda, Tohru Kawai, Atsushi Amo
  • Patent number: 12040813
    Abstract: An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: July 16, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichi Iizuka, Fukashi Morishita
  • Patent number: 12034394
    Abstract: A motor driver using a correcting mechanism on a sensed motor position is provided. A rotor position detector circuit senses a position of a rotor of a motor to output a commutation signal. A back electromotive force detector circuit detects a back electromotive force signal of the motor. An actual phase difference calculator circuit calculates a phase difference between the back electromotive force signal and the commutation signal as an actual phase difference. An error phase angle calculator circuit calculates a difference between the actual phase difference and a reference phase difference as an error phase angle. A motor driving circuit corrects the commutation signal according to the error phase angle. The motor driving circuit determines the position of the rotor of the motor to drive the motor according to the corrected commutation signal.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: July 9, 2024
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Kun-Min Chen
  • Patent number: 12015053
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion which is integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, a high dielectric constant film in contact with the step insulating film and having a higher dielectric constant than silicon.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: June 18, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Koshimizu, Yasutaka Nakashiba
  • Patent number: 12015020
    Abstract: Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: June 18, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takafumi Betsui
  • Patent number: 12013679
    Abstract: It is an object of the present invention to provide a technique capable of easily extracting a section signal of a specific sub-process. The anomaly detection system includes an extraction unit for extracting a specific subsequence to be an object of anomaly detection from among a plurality of subsequences from a composite sequence included in a monitor signal. The extraction unit determines an optimal warping path from the composite sequence and a reference sequence, which is an example of the composite sequence acquired in advance, by a dynamic time warping method. The extraction unit identifies a start point and an end point of a specific subsequence based on the optimal warping path and the start point and end point of the subsequence of the reference sequence. The extraction unit extracts a specific subsequence based on a start point and an end point of the specific subsequence.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 18, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shinji Ishikawa