Abstract: A circuit (1) is described for detecting a reverse current condition of a DCDC converter (2). This circuit uses a simple logic gate such as an AND gate to sense the voltage on a determined node (7) of the DCDC converter, and the propagation of the gated signal (27) is controlled using the timing control signals SW1 and SW2 of the DCDC converter, together with delay cells (16 and 17), to ensure that the positive or negative state of the sensed voltage at said node (7) is propagated cleanly through the logic gate (18), the flip-flop or latch circuit (19) and the up-down counter (29) to the output timing control circuit (25). The up-down counter is incremented or decremented in dependence on the presence or absence of a reverse current condition at said node, and the count value (24) of the up-down counter determines the duration of the on-period of the second-phase timing control signal SW2.

Abstract: The present invention concerns an electronic circuit comprising a control signal processing circuit with a control signal input and a control signal output circuit, the processing circuit being arranged to process a control signal applied to the control signal input, and to operate in at least one of a first power mode and a second power mode, the second power mode having a lower power consumption than the first power mode. The electronic circuit further comprises a control signal processing circuit bypass means for providing, when the processing circuit is in the second power mode, a bypass connection for conveying the control signal from the control signal input to the control signal output circuit, thereby bypassing the processing circuit.

Abstract: The electronic circuit (1) includes, in an automatic gain control loop, an input amplifier (2), an AGC unit connected to the amplifier output to detect the amplitude of an output signal and a unit (10) for attenuating an input signal of the amplifier based on an adaptation signal (VAGC) from the AGC unit. The attenuation unit includes a means of comparing the adaptation signal to a reference signal (VREF) and for supplying an attenuation current as a function of the difference between the adaptation and reference signals, to a diode-connected PMOS replica transistor (M2), which is connected by a source to a common mode voltage (VCM) dependent on the input signal of the amplifier. The replica transistor controls a PMOS shunt transistor (M1) defining a shunt resistance connected to the amplifier input, whose resistive value depends on the attenuation current passing through the replica transistor.

Abstract: The electronic circuit is arranged for the fast, automatic gain control of an input amplifier. It includes a non-linear amplifier-comparator for comparing a reference signal (VR) to an amplitude signal (VP) at the output of the input amplifier. The amplifier-comparator performs dual slope adaptation of the input amplifier gain according to a defined deviation threshold between the two input signals. The amplifier-comparator includes two branches each with three transistors connected in series between the terminals of a supply voltage source. First and second polarization transistors (M5, M6) are connected to the first and second input transistors (M1, M2) controlled by the first and second input signals, which are respectively connected to a first diode-connected transistor (M3) and a second transistor (M4) of a current mirror. A non-linear transconductance element (RNL) connects the sources of the input transistors to define a dual slope gain adaptation of the non-linear amplifier-comparator.

Abstract: A method adjusts a reference voltage of an electronic circuit based on a band-gap voltage supplied by a first band-gap stage. The band-gap stage includes in a series arrangement, between two terminals of a voltage supply source, a current source connected to a first branch, which includes a first configurable resistor in series with a first diode, and to a second branch, which includes a second configurable resistor connected to a complementary resistor in series with a second diode. The band-gap voltage is supplied to a connection node between the current source and each branch. The current source is a PMOS transistor controlled by an output voltage of a first operational amplifier of a current control loop.

Abstract: The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises a detector operable to analyze a temporal activity of the charge pump, and a pump clock generator coupled to an output of the detector and having an output coupled to a clock input of the charge pump to vary a pump clock frequency of the charge pump in dependence of the analysis of the detector, or a supply or voltage generator coupled to an output of the detector and having an output coupled to the charge pump to vary an amplitude of a clock signal within the charge pump in dependence of the analysis of the detector.

Abstract: The voltage regulator comprises a regulation loop (2), which comprises at least a pass transistor (18), a source transistor (28), a sensing transistor (22) and a retention transistor (24), and a stability compensation circuit (10), which comprises a first MOS resistor (12) and a second MOS resistor (14) coupled with the first MOS resistor (12). The gate of the second MOS resistor (14) is coupled to the gate of the pass transistor (18).

Abstract: A narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver includes an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop.

Abstract: The invention relates to a procedure for accessing a non-volatile watch memory, the watch comprising two supply terminals accessible from the outside that define a potential difference corresponding to a standard supply voltage, and a control circuit of the non-volatile memory produced using a technology supporting a predefined maximum supply voltage, the access procedure consisting of transmitting the following to the control circuit of the non-volatile memory by means of a supply terminal of the watch: a) an opening key to authorize access to the non-volatile memory; b) an instruction for access to the non-volatile memory; the procedure being characterized in that the opening key is a predefined instruction transmitted by modulation of the standard supply voltage such that this does not exceed the predefined maximum supply voltage.

Abstract: The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Abstract: The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises: a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.

Abstract: The random number generator comprises a linear feedback shift register (10), which comprises a series of storage elements (14(1), 14(2), . . . , 14(n)), a first input (11) to receive a clock signal from a clock oscillator (28), a feedback line (20) connecting the output of a last storage element (14(n)) with an input of at least a first storage element (14(1)), a second input (22) coupled with the feedback line (20) via at least one cell (15) and wherein the output of the cell (15) is coupled to an input of at least one of the storage elements (14(1), 14(2), . . . , 14(n)).

Abstract: The electronic circuit (1) is for driving a resonator (2) of a MEMS resonator device. The resonator includes a mass (m) connected to a spring (k) and a damping element (d), an actuation element (Cact) for actuating the mass via an actuation signal (drive), and a detection element (Cdet) for detecting motion of the mass. The electronic circuit includes a conversion means (3) connected to the detection element to supply a mass oscillation derivative signal (der), a means (4, 5, 6) of comparing the derivative signal amplitude and a reference amplitude (ref) for supplying a control signal (cmd), and a decision unit (7) for supplying a digital actuation signal (drive). The actuation signal includes rectangular pulses determined on the basis of the derivative signal and of the control signal to adapt the mass oscillation amplitude according to the reference amplitude.

Abstract: The automatic gain control unit for a radiofrequency receiver includes a first current source for charging a storage capacitor by a first current, four comparators for comparing on the lower side an in-phase positive intermediate signal, an in-phase negative intermediate signal, a quarter-phase positive intermediate signal, a quarter-phase intermediate signal with a first reference threshold to a high amplitude level of the intermediate signals. Each comparator controls a MOS transistor connected in series between a second current source and the storage capacitor in order to discharge the storage capacitor when each transistor is in a conductive state. A bi-stable trigger element is connected to the storage capacitor and to provide an AGC signal depending on the voltage level on the storage capacitor for attenuating or not the gain of the low noise amplifier or of a mixer unit amplifier of the receiver.

Abstract: Method for reading a barcode by means of an optical reader arranged to capture at a determined sampling frequency a series of partial images of the barcode by a sensor having at least one line of pixels. According to the invention it is provided to determine in each partial image a logical value as a function of the light intensity received by a central pixel of the line of pixels and a corresponding bar width when this bar is completely incorporated into the partial image in question. By only setting a maximum speed for the speed of movement of the barcode and dimensioning the line of pixels to ensure that each bar of this barcode is completely incorporated into a partial image at least once, the sequence of bits defined by the barcode is determined by means of an algorithm ignoring the duplications detected in consecutive partial images.

Abstract: The circuit is provided for the transmission of data amplitude modulated radio frequency signals. The circuit includes a local oscillator for generating an oscillating signal at a determined carrier frequency, a unit for shaping data pulses to supply a data amplitude modulation control signal (Vmod), and a power amplifier receiving the oscillating signal and the data amplitude modulation control signal (Vmod) for the transmission of data amplitude modulated radio frequency signals by an antenna or an antenna arrangement. The data pulse shaping unit (13) includes a pulse shaper (21) for digitally adapting the data transition edges on the basis of an incoming digital data signal (d), and a digital-analog conversion stage (26, 27) for converting a digital data signal shaped in the unit, in order to supply the data amplitude modulation control signal (Vmod) to the power amplifier.

Abstract: The invention relates to a measuring circuit comprising a control block for controlling said circuit, a time base for providing a clock signal (fclk) in order to time said circuit, a sensor block which is designed to provide an output signal, said measuring circuit comprising in addition a first counting block which is timed to the clock frequency and a second counting block which is timed by the frequency of the output signal of the sensor block.

Abstract: The present invention relates to a narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver comprises an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop.

Abstract: The present invention relates to a receiver circuit for processing of electrical signals, and comprising: an antenna (12), at least one amplifier (14) coupled to the output of the antenna (12), an automatic gain control circuit (30) coupled to the at least one amplifier (14) to modify a gain thereof, and at least one voltage offset-compensating circuit (50) embedded in the automatic gain control circuit (30) and comprising a clock generator (40) and at least one capacitor (42, 44) to effectively compensate an offset voltage.

Abstract: The automatic gain control unit for a radiofrequency receiver includes a first current source for charging a storage capacitor by a first current, four comparators for comparing on the lower side an in-phase positive intermediate signal, an in-phase negative intermediate signal, a quarter-phase positive intermediate signal, a quarter-phase intermediate signal with a first reference threshold to a high amplitude level of the intermediate signals. Each comparator controls a MOS transistor connected in series between a second current source and the storage capacitor in order to discharge the storage capacitor when each transistor is in a conductive state. A bi-stable trigger element is connected to the storage capacitor and to provide an AGC signal depending on the voltage level on the storage capacitor for attenuating or not the gain of the low noise amplifier or of a mixer unit amplifier of the receiver.