Abstract: An envelope detector circuit, suitable for use in RFID tags, includes a voltage doubler circuit and a biasing voltage generating circuit which comprises components matched respectively to rectifying components of the voltage doubler circuit. A rectifying component of this voltage doubler circuit is formed by a transistor controlled by the biasing voltage generating circuit which provides a biasing voltage to a control gate of this transistor, the biasing voltage generating circuit being arranged so as to permit a determined forward biasing current to flow through the transistor and further rectifying elements of the voltage doubler circuit. This embodiment provides fast, highly sensitive detection of envelope waveforms in input signals. Thanks to the matched rectifying components, efficiency variations due to variations in manufacturing process can be eliminated. The envelope detector circuit is further arranged for maintaining a stable detection independent of variations in temperature.

Abstract: The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

Abstract: A receiver circuit includes an input terminal through which an input signal is received. The receiver circuit also includes a first amplifier stage connected via its input to the input terminal of the receiver circuit; and an envelope detector stage that detects the incoming signal maxima to recover the signal envelope, where the detector stage is connected to the output of the first stage.

Abstract: The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Abstract: A method for measuring relative motion between an illuminated surface and an optical sensing device comprising a coherent light source and a photodetector array is described.

Abstract: A circuit configuration for secure application includes several internal frequency detectors arranged in digital units at critical points of an integrated circuit. The clock detectors are concealed in the digital part of the integrated circuit each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.

Abstract: This concerns a Bluetooth Low Energy (BLE) device, or system, or method of operating a BLE device and a respective computer program. The BLE device comprises a transceiver to broadcast the at least one advertising packet, a processor connected to the transceiver to generate the advertising packet and/or to trigger broadcasting thereof according to a broadcasting schedule. The device further comprises a verification element connected to the processor and being capable of ascertaining if a predefined condition is met, at least one of the verification element and the processor is capable of modifying the broadcasting schedule based on the predefined condition's ascertainment.

Abstract: The present invention concerns an electronic measurement circuit for measuring a physical parameter. The circuit comprises: a measurement sensor comprising two differential mounted capacitors each comprising a fixed electrode, and a common electrode, common to the two capacitors which is arranged to be movable relative to each fixed electrode of the two capacitors in order to alter the capacitive value of each capacitor when the physical parameter is measured.

Abstract: The physical parameter measurement method is performed using an electronic circuit (1) with a resistive sensor (2). The resistive sensor includes two resistors (R1, R2) mounted in series, whose connection node connected to a moving mass (M), is connected to a first input of an amplifier-comparator (3). A second input of the amplifier-comparator receives a reference voltage. One output of the amplifier-comparator is connected to a logic unit (4), which provides a digital output signal (OUT). A digital-to-analogue converter (5) provides a measurement voltage (Vdac), as a function of a digital signal provided by the logic unit, to the first resistor (R1) in a first phase of a measurement cycle, whereas the second resistor (R2) is polarized by a polarization voltage, and to the second resistor in a second phase, whereas the first resistor is polarized by a polarization voltage via a switching unit.

Abstract: The voltage regulator comprises a regulation loop (2), which comprises at least a pass transistor (18), a source transistor (28), a sensing transistor (22) and a retention transistor (24), and a stability compensation circuit (10), which comprises a first MOS resistor (12) and a second MOS resistor (14) coupled with the first MOS resistor (12). The gate of the second MOS resistor (14) is coupled to the gate of the pass transistor (18).

Abstract: The present invention relates to a method, to a computer program and to a system to establish wireless communication between at least two Bluetooth Low Energy (BLE) devices the method comprising the steps of: switching a first BLE device (20) into a scanning mode (SM), switching a second BLE device (30) into an advertising mode (AM), and broadcasting a first advertising packet (31) from the second BLE device, switching the second BLE device (30) into the scanning mode (SM), receiving the first advertising packet (31) by first BLE device (20), and switching the first BLE device (20) into the advertising mode (AM), and broadcasting a second advertising packet (21) from the first BLE device (30).

Abstract: The smart battery (1) includes an electronic module provided with an electronic circuit (8) for controlling the supply voltage, which is disposed in a case having a cover (2) as the external negative terminal, fixed to a cup (3), as the external positive terminal. A first chemical substance (4) as the anode and a second chemical substance (5) as the cathode, are inside the case. The electronic module includes a printed circuit board (7) having a first face with conductive paths, connected to the electronic circuit, and a second insulating face fixed to the second chemical substance. The electronic circuit is connected at output to a first connection pad connected to the cup. The electronic circuit is connected to the chemical substances by a second connection pad on a first tab (7?) and by a third connection pad on a second tab (7?) folded at 180° on the second face of the printed circuit board.

Abstract: A customer medium (1) for detecting the utilization of services is proposed, comprising a first and a second antenna (2, 3) for long-range data communication, a third antenna (4), an integrated circuit (6) comprising at least one crypto-engine, one microprocessor (5) connected with the integrated circuit (6) or integrated into the integrated circuit (6), an operational amplifier (8) and an RF transceiver (7) connected to the second antenna (3), where the third antenna (4) is connected to an NFC-module in the integrated circuit (6) and is used for the short-range data communication in an active mode of the customer medium (1), where the first antenna (2) is used as a wake-up antenna for receiving an amplitude-modulated wake-up signal if the customer medium is in a “sleep” mode, where the signal received by the wake-up antenna (2) is demodulated and amplified by the operational amplifier (8) serving as the wake-up detection module and is evaluated by the microprocessor (5) partially activated in the “sleep” mod

Abstract: The present invention concerns a method of operating a first-in first-out memory (9) arranged to store measurement data samples measured by a plurality of data measurement sensors (1, 3, 5), which can operate at various sampling rates. The oldest measurement data sample in the memory (9) is arranged to be read first before the newer measurement data samples. The method comprises: receiving measurement data samples from at least two data measurement sensors (1, 3, 5); and saving the received measurement data samples in the memory (9). Each of the measurement data samples saved in the memory is associated with a tag which is also saved in the memory (9) and which identifies the data measurement sensor (1, 3, 5) which measured the respective measurement data sample.

Abstract: The present invention concerns a mutual authentication method in a communication system. According to the method, a first communication device (1), such as an RFID reader, authenticates a second communication device (3), such as an RFID tag, by using an asymmetric authentication protocol based on a generated a session key. The tag authenticates the reader by using a symmetric communication protocol based on a generated other session key. At least a portion of the session key is used to generate the other session key.

Abstract: The present invention relates to a fault detection assembly of an integrated circuit having a supply port, an input port and a ground port. The fault detection assembly comprises a first diode connected with one end to the supply port and connected with the other end to the input port, a second diode connected with one end to the input port and connected with the other end to the ground port, at least a first fault detection transistor of MOS type. At least one of first and second diodes comprises a first diode-connected MOS transistor whose gate is connected to the gate of the first fault detection transistor.

Abstract: A physical parameter is measured via an electronic circuit connected to a two capacitor sensor. The circuit includes an amplifier connected to the common capacitor electrode, a logic unit for digital processing amplifier data and supplying a digital measuring signal, a digital-analog converter for supplying a measuring voltage based on the digital measuring signal, a switching unit for alternately supplying the measuring voltage to the first and second fixed capacitor electrodes, and a regulated voltage for negative biasing or a low voltage for positive biasing from a voltage supply source. A first phase consists in biasing the first fixed electrode with the measuring voltage from first binary word and reference voltage, and the second fixed electrode with low voltage, and a second phase consists in biasing the second fixed electrode with measuring voltage from second binary word, which is reverse of the first binary word, and the reference voltage.

Abstract: Organic light emitting diode display device including a substrate covered by a cover which has a plane surface delimited along the external perimeter thereof. The plane surface of the cover is provided with a protuberance. The substrate is provided with a stack of layers, the stack of layers including at least the following layers in succession in the following order starting from the substrate: at least one anode; an insulating layer; a spacer layer which has a first exclusion area in a first area; an active hole injection layer, an active hole transport layer and an active electron transport layer; a cathode layer which has a second exclusion area. The protuberance of the cover is joined to the layer with which the protuberance is in contact, a hole, whose diameter is smaller than the geometrical dimensions of the protuberance, being made in the protuberance and through the substrate.

Abstract: A method for reducing the non-linearity effect of a digital-analog converter on an electronic interface circuit of a capacitive sensor. The electronic circuit includes an amplifier connected to the common electrode by a switching unit, a logic unit connected to the amplifier for supplying first and second digital measuring signals, and a digital-analog converter for supplying a measuring voltage to the electrodes. The method includes firstly biasing the capacitor electrodes by the measuring voltage, then biasing the fixed electrode of the first capacitor at a regulated voltage and the fixed electrode of the second capacitor at a low voltage, then biasing the capacitor electrodes by the measuring voltage, and finally biasing the fixed electrode of the first capacitor at a low voltage and the fixed electrode of the second capacitor at a regulated voltage.

Abstract: The method is for measuring a physical parameter by an electronic circuit connected to a two differential capacitor sensor having two fixed electrodes and a common moving electrode. The electronic circuit supplies first and second digital measuring signals. Each measuring cycle consists on biasing the electrodes by the measuring voltage based on the first digital signal, connecting the fixed electrodes to a supply voltage source for a first biasing, biasing the electrodes by the measuring voltage based on the second digital measuring signal, and inversely connecting the fixed electrodes to a supply voltage source for a second biasing. In first successive measuring cycles, the first and second digital signals are adapted to each cycle by a large step value. In second successive measuring cycles, the first and second digital signals are adapted to each cycle by a small step value until the end of the conversion.