Abstract: The present invention relates to a receiver circuit for processing of electrical signals, and comprising: an antenna (12), at least one amplifier (14) coupled to the output of the antenna (12), an automatic gain control circuit (30) coupled to the at least one amplifier (14) to modify a gain thereof, and at least one voltage offset-compensating circuit (50) embedded in the automatic gain control circuit (30) and comprising a clock generator (40) and at least one capacitor (42, 44) to effectively compensate an offset voltage.

Abstract: Process for adjusting a time base by inhibiting clock pulses supplied by a clock circuit, this adjustment process comprising the following steps: selecting an inhibition period; determining a first number N of clock pulses to be suppressed per inhibition period to adjust over each inhibition period the number of clock pulses activating a frequency divider circuit such that the frequency of the time base comes closest to a reference unit frequency; selecting a plurality K of sub-periods for each inhibition period; suppressing in each sub-period a second number N1 of clock pulses corresponding to the result of the integral division of the first number by the number of sub-periods, and in addition to the suppression of the preceding step, suppressing in each inhibition period a third number N2 of clock pulses corresponding to the remainder of said integral division.

Abstract: The electronic circuit is arranged for the fast, automatic gain control of an input amplifier. It includes a non-linear amplifier-comparator for comparing a reference signal (VR) to an amplitude signal (VP) at the output of the input amplifier. The amplifier-comparator performs dual slope adaptation of the input amplifier gain according to a defined deviation threshold between the two input signals. The amplifier-comparator includes two branches each with three transistors connected in series between the terminals of a supply voltage source. First and second polarisation transistors (M5, M6) are connected to the first and second input transistors (M1, M2) controlled by the first and second input signals, which are respectively connected to a first diode-connected transistor (M3) and a second transistor (M4) of a current mirror. A non-linear transconductance element (RNL) connects the sources of the input transistors to define a dual slope gain adaptation of the non-linear amplifier-comparator.

Abstract: The electronic circuit (1) includes, in an automatic gain control loop, an input amplifier (2), an AGC unit connected to the amplifier output to detect the amplitude of an output signal and a unit (10) for attenuating an input signal of the amplifier based on an adaptation signal (VAGC) from the AGC unit. The attenuation unit includes a means of comparing the adaptation signal to a reference signal (VREF) and for supplying an attenuation current as a function of the difference between the adaptation and reference signals, to a diode-connected PMOS replica transistor (M2), which is connected by a source to a common mode voltage (VCM) dependent on the input signal of the amplifier. The replica transistor controls a PMOS shunt transistor (M1) defining a shunt resistance connected to the amplifier input, whose resistive value depends on the attenuation current passing through the replica transistor.

Abstract: The present invention concerns a receiver circuit including an input terminal through which an input signal is received, said receiver circuit further including: a first amplifier stage connected via its input to the input terminal of said receiver circuit; an envelope detector stage for detecting the incoming signal maxima to recover the signal envelope, said detector stage being connected to the output of the first stage.

Abstract: An RFID transponder chip includes at least one antenna to pick-up and transmit radio-frequency signals, a rectifier to store charge on at least one capacitor at a rectified voltage from the picked-up radio-frequency signals, a power-on reset circuit to maintain a logic unit in a reset state if the rectified voltage level is less than a power-on reset or wake-up voltage of the power-on reset circuit for operating the logic unit. The RFID transponder chip further includes a non-volatile memory, in which are stored one or several trim values. Said non-volatile memory is directly connected to the power-on reset circuit to be able to provide at least one trim value to trim the power-on reset circuit at a rectified voltage level below a wake-up voltage level.

Abstract: A half-duplex passive transponder including: a resonant circuit including an antenna and input capacitor and configured to allow an electrical signal to oscillate in the resonant circuit when periodically receiving across the antenna an activation signal from a reader; at least one switch between the input capacitor and a storage capacitor so the two capacitors are in parallel when the switch is turned on; a peak voltage detector configured to measure amplitude of the electrical signal oscillating in the resonant circuit; and a variable voltage threshold determination circuit configured to trigger each of plucking pulses when voltage of the oscillating electrical signal substantially attains a variable voltage threshold in a respective period before an extremum of the oscillating electrical signal and in a half-cycle of the extremum, to thus deliver plucking pulses during a transmission period in the resonant circuit to maintain a certain amplitude of the oscillating electrical signal.

Abstract: The invention concerns a test method for a transmitter-receiver circuit. This transmitter-receiver circuit includes an antenna, connected to a processing unit, arranged for receiving signals and converting their frequency. The transmitter-receiver circuit also includes a power amplifier connected to said antenna and arranged for sending transmission signals.

Abstract: The electronic circuit has a capacitive sensor that includes two capacitors mounted in differential, whose common electrode can move relative to each fixed electrode of the two capacitors to alter the capacitive value of each capacitor. The electronic circuit has an interface connected to the capacitive sensor, which includes a charge transfer amplifier unit connected to the common electrode, an integrator unit, and an excitation unit arranged between the output of the first integrator unit and the sensor to polarise each fixed electrode of the sensor capacitors at a determined voltage value. A compensation capacitor is connected to the input of the integrator unit. The electronic circuit interface includes comparison means for comparing the output voltage with a comparison voltage to control disconnection of the compensation capacitor at the integrator unit input, if the deviation between the output voltage and the comparison voltage exceeds a determined voltage threshold.

Abstract: A RFID transponder includes an electronic circuit and an antenna, the electronic circuit being integrated in a p-type substrate and comprising a modulator formed by a PMOS transistor whose drain, electrically connected to a pad of the antenna, and source, connected to the ground of the electronic circuit, are arranged in an n-type well provided in the p-type substrate. The PMOS transistor has a gate driven by a driving circuit which is arranged for providing at least a negative voltage, this negative voltage being low enough for turning on this PMOS transistor in response to a control signal provided by a logical unit of the electronic circuit.

Abstract: An RFID transponder chip includes at least one antenna to pick-up and transmit radio-frequency signals, a rectifier to store charge on at least one capacitor at a rectified voltage from the picked-up radio-frequency signals, a power-on reset circuit to maintain a logic unit in a reset state if the rectified voltage level is less than a power-on reset or wake-up voltage of the power-on reset circuit for operating the logic unit. The RFID transponder chip further includes a non-volatile memory, in which are stored one or several trim values. Said non-volatile memory is directly connected to the power-on reset circuit to be able to provide at least one trim value to trim the power-on reset circuit at a rectified voltage level below a wake-up voltage level.

Abstract: A physical parameter is measured via an electronic circuit connected to a two capacitor sensor. The circuit includes an amplifier connected to the common capacitor electrode, a logic unit for digital processing amplifier data and supplying a digital measuring signal, a digital-analogue converter for supplying a measuring voltage based on the digital measuring signal, a switching unit for alternately supplying the measuring voltage to the first and second fixed capacitor electrodes, and a regulated voltage for negative biasing or a low voltage for positive biasing from a voltage supply source. A first phase consists in biasing the first fixed electrode with the measuring voltage from first binary word and reference voltage, and the second fixed electrode with low voltage, and a second phase consists in biasing the second fixed electrode with measuring voltage from second binary word, which is reverse of the first binary word, and the reference voltage.

Abstract: A method performs a comparison of input signals in a window comparator circuit. In a first phase, input, ground and offset voltages are stored on capacitors. A comparison is performed between a first adapted input voltage and a second adapted input voltage added to an adapted offset voltage, to provide a first output signal. In a second phase, the voltages are stored on the capacitors in a different manner. A comparison is performed between the first adapted input voltage added to the adapted offset voltage and the second adapted input voltage, to provide a second output signal. Finally, a control of the state of the output signals is performed to determine if the comparison is in a low or high state if the output signals have a same low or high output level, or in an intermediate state if the output signals have a different output level.

Abstract: The electronic circuit is intended to form with an antenna a responder that operates without resetting to zero when the power supply of the electronic circuit is switched on (without POR). To increase efficiency and reduce the costs of testing a plurality of such integrated circuits in a wafer, means are provided that allow the logic circuit (8) to be reset to zero during such a test by electrical contact with the pads (P1, P2) of each circuit by using two extractors (12 and 14) of clock signals (CL1 and CL2) connected to the inputs of a generator (20) of a zero reset signal (SR). The state of the generator is essentially given by the difference in pulses received from the two clock signal extractors. As soon as the state of the generator corresponds to a value equal to or greater than a predefined integer, the logic circuit is reset to zero, which never occurs with the responder receiving an interrogation signal of a reader.

Abstract: The method is for measuring a physical parameter by an electronic circuit connected to a two differential capacitor sensor having two fixed electrodes and a common moving electrode. The electronic circuit supplies first and second digital measuring signals. Each measuring cycle consists on biasing the electrodes by the measuring voltage based on the first digital signal, connecting the fixed electrodes to a supply voltage source for a first biasing, biasing the electrodes by the measuring voltage based on the second digital measuring signal, and inversely connecting the fixed electrodes to a supply voltage source for a second biasing. In first successive measuring cycles, the first and second digital signals are adapted to each cycle by a large step value. In second successive measuring cycles, the first and second digital signals are adapted to each cycle by a small step value until the end of the conversion.

Abstract: The method is for measuring a physical parameter via an electronic circuit connected to a two differential capacitor sensor having two fixed electrodes and a common moving electrode. The circuit supplies first and second digital measuring signals. Each measuring cycle consists on biasing fixed electrodes by a first biasing and a second biasing reverse of the first biasing, alternated with biasing the electrodes by the measuring voltage based on first and second digital signals. Each conversion starts by a small step value added to or subtracted from each digital signal in each cycle. If the successive identical amplifier output states counted or counted down by a counter is higher than a threshold, a large step value is added to or subtracted from the digital signals in each cycle. Re-adaptation to the small step value occurs when a sign change is detected in the counter, until the conversion end.

Abstract: A method performs a comparison of input signals in a window comparator circuit. In a first phase, input, ground and offset voltages are stored on capacitors. A comparison is performed between a first adapted input voltage and a second adapted input voltage added to an adapted offset voltage, to provide a first output signal. In a second phase, the voltages are stored on the capacitors in a different manner. A comparison is performed between the first adapted input voltage added to the adapted offset voltage and the second adapted input voltage, to provide a second output signal. Finally, a control of the state of the output signals is performed to determine if the comparison is in a low or high state if the output signals have a same low or high output level, or in an intermediate state if the output signals have a different output level.

Abstract: The active transponder includes an input amplifier (26) arranged between an envelope detector (8) and a demodulation circuit (28). It further includes an activation unit (30) for the input amplifier and also for the demodulation circuit, which is formed by a frequency changer or mixer circuit (32), which decreases a significant modulation frequency of the modulated signal received by the antenna to a low frequency, the resulting low frequency signal then being amplified and filtered by low frequency elements. The activation unit thus consumes little electric power and sends a wake up signal to the elements operating at a high frequency when it detects said significant modulation frequency, in a very selective manner.

Abstract: The circuit is provided for the transmission of data amplitude modulated radio frequency signals. The circuit includes a local oscillator for generating an oscillating signal at a determined carrier frequency, a unit for shaping data pulses to supply a data amplitude modulation control signal (Vmod), and a power amplifier receiving the oscillating signal and the data amplitude modulation control signal (Vmod) for the transmission of data amplitude modulated radio frequency signals by an antenna or an antenna arrangement. The data pulse shaping unit (13) includes a pulse shaper (21) for digitally adapting the data transition edges on the basis of an incoming digital data signal (d), and a digital-analogue conversion stage (26, 27) for converting a digital data signal shaped in the unit, in order to supply the data amplitude modulation control signal (Vmod) to the power amplifier.

Abstract: The Installation is equipped with a power supply unit and a High-Definition Multimedia Interface (HDMI), this installation being able to be connected to a second HDMI device with which it can communicate by using a protocol defined in the HDMI Standard, this installation or device being able to be set in Standby or Power-down mode and to be removed from this Standby or Power-down mode by said second HDMI device via a Consumer Electronic Control (CEC) line. The installation has a Power Management Unit (PMU) arranged on the primary side of said power supply unit, this PMU having its own power supply circuit directly connected to the power supply source of this installation or device and being arranged for switching OFF the electrical energy on the secondary side of said power supply unit when this installation or device enters said Standby or Power-down mode.