Abstract: A power distribution system and method may include a first power domain having a first plurality of power rails, a second power domain having a second plurality of power rails, where the first power domain is electrically independent of the second power domain, and a plurality of modules coupled to the first power domain and the second power domain, where each of the plurality of modules is coupled to one of the first plurality of power rails and one of the second plurality of power rails. The system may also include a plurality of mated pairs, where each of the plurality of modules is in only one of the plurality of mated pairs, and where each of the plurality of mated pairs is coupled to two separate of the first and second plurality of power rails.
Type:
Grant
Filed:
November 28, 2005
Date of Patent:
July 1, 2008
Assignee:
Emerson Network Power - Embedded Computing, Inc.
Inventors:
Mark S. Lanus, Bruce A. Hanahan, Wolfgang Poschenrieder
Abstract: A power distribution unit (306) may include a power distribution unit frame (310), where the power distribution unit frame has a 2U form factor (312), and where the power distribution unit frame is coupled to mount in an embedded computer frame (102). A plurality of power ingress sites (330) may be coupled to a rear portion (320) of the power distribution unit frame, where each of the plurality of power ingress sites has a current capacity of at least 100 amperes, where each of the plurality of power ingress sites includes an ingress pin (332) coupled to interface with an ingress in-line, hyperboloid radial socket (334), and where the power distribution unit has a current-capacity density of the plurality of power ingress sites of at least 600 amperes per power distribution unit.
Type:
Grant
Filed:
March 30, 2005
Date of Patent:
July 1, 2008
Assignee:
Emerson Network Power - Embedded Computing, Inc.
Inventors:
John H. Kelly, Naufel C. Naufel, Irena Borucki, Eugene R. Pilat, Markus Tegethoff
Abstract: A method of electroplating may include placing a pair of conductive fingers in proximity to an edge of a circuit board, where the pair are coupled to be electrically isolated, and where the pair are substantially longitudinally oriented away from the edge. A trace electrically couples the pair of conductive fingers via a shortest path between the pair of conductive fingers. A plating bar is electrically coupled to one of the pair of conductive fingers and thereafter electroplating the pair of conductive fingers via the plating bar. Subsequent to electroplating, laser drilling the trace to electrically isolate the pair of conductive fingers.
Type:
Application
Filed:
March 12, 2008
Publication date:
June 26, 2008
Applicant:
EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.
Abstract: A subrack having a front side and a rear side, wherein the subrack is coupled to receive an Advanced Mezzanine Card module, the subrack includes a monolithic backplane having a first portion and second portion, where the first portion runs substantially along the front side and the second portion runs substantially along the rear side. A first slot is to receive the Advanced Mezzanine Card module inserted via the front side and connect the Advanced Mezzanine Card module directly to the second portion of the monolithic backplane. A second slot is to receive the Advanced Mezzanine Card module inserted via the rear side and connect the Advanced Mezzanine Card module directly to the first portion of the monolithic backplane.
Type:
Grant
Filed:
November 28, 2005
Date of Patent:
June 17, 2008
Assignee:
Emerson Network Power - Embedded Computing, Inc.
Abstract: A method of latent fault checking a cooling module of an embedded computer chassis may include prior to detection of an active fault in the cooling module, performing a fan controller latent fault checking algorithm and a full-speed latent fault checking algorithm. The fan controller latent fault checking algorithm may include attempting to modify a fan speed in the cooling module via a fan controller module in the cooling module, and determining if a change in the fan speed is detected. The full-speed latent fault checking algorithm may include attempting to modify the fan speed via a full speed fan control circuit, bypassing the fan controller module, and determining if the change in the fan speed is detected. If the change in the fan speed is not detected in at least one of the fan controller latent fault checking algorithm and the full-speed latent fault checking algorithm, a latent fault in the cooling module of the embedded computer chassis may be indicated.
Type:
Grant
Filed:
January 20, 2006
Date of Patent:
May 13, 2008
Assignee:
Emerson Network Power - Embedded Computing, Inc.
Abstract: A rear transition module (220) includes a connector (230) in an RP0 mechanical envelope (242), and an RTM alignment and keying mechanism (232) in the RP0 mechanical envelope of the rear transition module that uniquely corresponds to a first signal path configuration (363) in a corresponding connector (234) on a backplane (202) of a VXS multi-service platform system chassis (103), where the rear transition module is coupled to operate within the VXS multi-service platform system chassis having a VMEbus network (108) and a switched fabric (110) coincident on the backplane.
Type:
Grant
Filed:
July 13, 2004
Date of Patent:
May 6, 2008
Assignee:
Emerson Network Power-Embedded Computing, Inc.
Abstract: A method of electroplating may include placing a pair of conductive fingers in proximity to an edge of a circuit board, where the pair are coupled to be electrically isolated, and where the pair are substantially longitudinally oriented away from the edge. A trace electrically couples the pair of conductive fingers via a shortest path between the pair of conductive fingers. A plating bar is electrically coupled to one of the pair of conductive fingers and thereafter electroplating the pair of conductive fingers via the plating bar. Subsequent to electroplating, laser drilling the trace to electrically isolate the pair of conductive fingers.
Type:
Grant
Filed:
February 27, 2006
Date of Patent:
April 1, 2008
Assignee:
Emerson Network Power - Embedded Computing, Inc.