Abstract: A system and method for providing access to a Logical Unit mapped to an iSCSI target are described herein. In accordance with this disclosure, an initiator IQN name may be split into a physical IQN name (PIN) and a virtual IQN name (VIN). The VIN may be assigned to a virtual adapter that is created in a guest partition. The PIN may be assigned to a physical adapter (e.g., an iSCSI initiator in a hypervisor). The physical adapter may log into the iSCSI target on behalf of the virtual adapter using the VIN. The physical adapter may receive a list of available logical units associated with the iSCSI target and map the list of available logical units to the virtual adapter. Thereafter, a quality of service between the virtual adapter and the iSCSI target may be monitored.

Abstract: The current document is directed to offloading communications processing from server computers to hardware controllers, including network interface controllers. In one implementation, the transport channel and zero, one, or more protocol channels immediately overlying the transport channel of a Windows Communication Foundation communications stack are offloaded to a network interface controller. The offloading of communications processing carried out by the methods and systems to which the current document is directed involves minimal supporting development and is configurable, during service-application initialization, by exchange of relatively small amounts of information between an enhanced NIC and the communications stack.

Abstract: When interfacing with a host, a networking device can handle a first data like Bulk Data Receive. The networking device can receive the first data and read a first queue entry from a receive queue in the host memory. In response to the read first queue entry, the networking device can write the first data to an unpinned memory in the host memory. The networking device can also handle a second data with a Receive Packet in Ring (RPIR) queue. The networking device can receive the second data and write the second data to a pinned memory in the host memory. The RPIR queue can be separate from or overlaid on the receive queue. High throughput and low-latency operation can be achieved. The use of a RPIR queue can facilitate the efficiency of resource utilization in the reception of data messages.

Abstract: Network virtualization can be provided via network I/O interfaces, which may be partially or fully aware of the virtualization. Network virtualization can be reflected in the use of a first header and an additional header(s) for a data frame. A partially-aware transmit example can gather together data frame components, including its additional header(s), via a work queue entry. A fully-aware transmit example can refer to a transmit-side table to gather its additional header(s) and can track the state of its additional header(s) stored in a cache. A partially-aware receive example can handle an additional header(s), e.g., by writing it to host-memory. A fully-aware receive example can determine values from multiple headers (including its additional header(s)) to further determine where to write a data payload to host-memory. The examples can relieve a host's hypervisor from performing all the network virtualization processing. The fully-aware examples can incorporate JOY techniques.

Abstract: When interfacing with a host, a networking device can handle a first data like Bulk Data Send. In response to a first doorbell ring, the networking device can read a first queue entry from a send queue in the host. Based on the first queue entry, the networking device can read the first data from a first memory in the host and then output the read first data. The networking device can also handle a second data like Direct Packet Push. The networking device can store a second data received from the host. In response to a second doorbell ring, the networking device can output the second data. The first data and the second data can be associated with first and second queue entries, both on the same send queue in the host. High-throughput and low-latency can be achieved. Small and large data packets can be accommodated.

Abstract: A scheduler is disclosed. The scheduler can include a time-wheel structure configured to hold scheduling elements, an enqueuer configured to place a scheduling element on the time-wheel structure, and a delay manager configured to direct the scheduling element through the time-wheel structure and remove the scheduling element from the time-wheel structure. The time-wheel structure can include a plurality of decades that can rotate, and each of the plurality of decades can rotate respectively at one or more different rates of rotation. Multiple scheduling elements can be on the time-wheel structure at least partially during the same time. The scheduling elements can be on different decades or on the same decade. One of the plurality of decades can comprise an entry configured to hold a plurality of scheduling elements.

Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.

Abstract: The collection of performance data at multiple servers in a SAN and forwarding that data to a centralized server for analysis is disclosed. Remote agents and a central server application collect specific interesting negative event data to enable a picture of the operational health of the SAN to be determined. The agents are placed in servers having HBAs acting as initiators. The agents interact with the HBAs through a driver stack to collect event data. Because of the initiator function they perform, HBAs have visibility to parts of the network that other entities do not have access to, and thus are ideal locations for gathering event data. A SAN diagnostics manager then pulls the collected data from each agent so that a “picture” of the SAN can be developed. In addition to collecting initiator data, the agents also collect errors and performance data from the OS of the servers.

Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.

Abstract: A system and method for connecting Ethernet networks is provided. The system includes a port, a port control module, and a connectivity module. The port control module supports a first link speed and can transfer data to ports that support a second or third link speed. The connectivity module can affect the transfer of data between the first port and at least one other port. The connectivity module supports a fixed data transfer rate.

Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.

Abstract: The collection of performance data at multiple servers in a SAN and forwarding that data to a centralized server for analysis is disclosed. Remote agents and a central server application collect specific interesting negative event data to enable a picture of the operational health of the SAN to be determined. The agents are placed in servers having HBAs acting as initiators. The agents interact with the HBAs through a driver stack to collect event data. Because of the initiator function they perform, HBAs have visibility to parts of the network that other entities do not have access to, and thus are ideal locations for gathering event data. A SAN diagnostics manager then pulls the collected data from each agent so that a “picture” of the SAN can be developed. In addition to collecting initiator data, the agents also collect errors and performance data from the OS of the servers.

Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.

Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: Embodiments of the invention are directed to automatically populating a database of names and secrets in an authentication server by sending one or more lists of one or more names and secrets by a network management software to an authentication server. Furthermore, some embodiments provide that the lists being sent are encrypted and/or embedded in otherwise inconspicuous files.

Abstract: Embodiments of the invention relate to performing network communications according to an existing protocol by using frames that are larger than those usually allowed by the existing protocol. Thus, embodiments of the present invention provide for an extension of the existing protocol which allows for the use of larger frames. Embodiments provide for use of various negotiation and initialization mechanisms of the existing protocol with additional modifications to allow for the negotiation of the use of larger frames. Some embodiments ensure that the negotiations are performed in such a manner that devices that feature the improvements of the present invention can communicate with devices that do not feature these improvements.

Abstract: This invention relates to error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: Embodiments of the invention are directed to automatically populating a database of names and secrets in an authentication server by sending one or more lists of one or more names and secrets by a network management software to an authentication server. Furthermore, some embodiments provide that the lists being sent are encrypted and/or embedded in otherwise inconspicuous files.

Abstract: A method for managing power consumption by a network device is disclosed. The network device includes first and second ports, each of the first and second ports identified by a unique identifier and adapted to handle separate network traffic. The method includes verifying that the first and the second ports are connected to a common network end node; shutting off a link between the first port and the network end node; obtaining the unique identifier of the first port; creating, on the second port, a virtual port in response to the unique identifier of the first port; discovering the virtual port on the network device; and redirecting traffic formerly routed through the link through the virtual port.

Abstract: Disclosed herein is a method allowing an existing or legacy network device to recognize and parse packets defined in accordance with future-defined standards without having to be re-configured to be compatible with such standards. In particular, the device can skip past unknown or newly-inserted fields, such as tag headers in a tagged packet, to parse and process the remainder of the packet. By skipping those added fields such as a tag header, the device can accommodate various future-defined standards without incurring additional engineering or design costs or compromising packet processing efficiency.