Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract: Generalized queues and specialized registers associated with the generalized queues are disclosed for coordinating the passing of information between two tightly coupled processors. The capacity of the queues can be adjusted to match the current environment, with no limit on the size of the entry as agreed upon between the sending and receiving processors, and with no practical limit on the number of entries or restrictions on where the entries appear. In addition, the specialized registers allow for immediate notifications of queue and other conditions, selectivity in receiving and generating conditions, and the ability to combine data transfer and particular condition notifications in the same attention register.

Abstract: The buffering of RSCN frames is disclosed so that RSCN traffic can be reduced. At the start of a state change notification period, a timer is started. A state change manager buffers state changes in a register that holds a pending RSCN frame by storing the address of each changed device. When a new state change is received, the address of the corresponding device is compared against each of the addresses currently stored in the buffered RSCN frame. If a duplicate address is found, the searching process ends. If no duplicate address is found, then the new address is added to the next available 32-bit field in the buffered RSCN frame. When a specified number of state changes have been received, or a specified amount of time has elapsed, the RSCN frame is sent to each initiator that had previously registered to receive state changes.

Abstract: Embodiments of the present invention are directed to controlling device access fairness in frame-based switches by automatically and continuously counting the number of actively communicating devices connected to each port and the type of devices connected to each port, and adjusting fairness accordingly. During a sampling window, the number of active devices and the type of devices connected to each port is determined. At the start of each fairness window, a weighted number of slots are assigned to each port based on the number of active devices connected to each port and the type of devices connected to that port. Within a single fairness window, each port is able to provide device accesses to the frame-based switch in accordance with the number of slots assigned to that port.

Abstract: A method for maintaining configurable and dynamically adjustable per-channel local port/bypass port access ratios in the multiple SOCs within an SPI-attached frame-based switch enclosure to improve the access fairness of devices upstream from the destination device is disclosed. A frame-based switch enclosure may include multiple SPI-attached SOCs, each SOC containing a plurality of ports, with one or more devices connected to each port and one virtual channel assigned to each port. Given a frame-based switch enclosure with N SOCs, the local port/bypass port access ratio for a particular SOC and a given virtual channel, where the particular SOC is M hops away from the SOC having a port corresponding to the given virtual channel and M>0, is 1:(N?M?1), while the local port/bypass port access ratio for the SOC (and the given virtual channel) having the port corresponding to the given virtual channel (i.e. the SOC for which M=0) is 0:0.

Abstract: The discovery and configuration of devices of interest connected to the Ethernet by an Ethernet port is disclosed. To perform discovery, Client software in a management interface transmits packets including the address of the management interface and a port identifier to a known broadcast address, requesting the MAC address for all devices of interest. Server software in the devices of interest parse the broadcast packets and broadcast a packet containing a MAC address that uniquely identifies the devices of interest back to the Client. Once the MAC addresses are returned to the Client, the Client can then broadcast protocol packets requesting the configuration of a specific device of interest such as a new IP address. Once a device of interest is configured with at least an IP address, the device of interest can communicate using TCP/IP, and it can thereafter be managed using higher level tools and firmware.

Abstract: The preferred embodiment of present invention is directed to an improved method and system for buffering incoming/unsolicited data received by a host computer that is connected to a network such as a storage area network. Specifically, in a host computer system in which the main memory of the host server maintains a I/O control block command ring, and which a connective port (e.g., a host bus adaptor) is operatively coupled to the main memory for handling I/O commands received by and transmitted from the host server, a host buffer queue (HBQ) is maintained for storing a series of buffer descriptors retrievable by the port for writing incoming/unsolicited data to specific address locations within the main memory.

Abstract: A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent transactions, can be accommodated by the FIFO memory (i.e., multiplexing between different sources that transmit in distributed bursts). The transfer length requirements associated with the ongoing data transfers are tracked, along with the total available space in the FIFO memory. A programmable buffer zone also can be included in the FIFO memory for additional overflow protection and/or to enable dynamic sizing of FIFO depth.

Abstract: The detection, removal and reinsertion of possibly malfunctioning devices from an arbitrated loop is disclosed. When a new device is first connected to a storage switch and a loop is formed and begins initialization, a LOOP_DOWN event is sent to a processor and a loop down timer is started for each port in the loop. If initialization is successful, a LOOP_UP event is sent to the processor and the loop down timer is reset for each port in the loop. However, if one of the loop down timers times out, a problem occurred during the initialization. The port associated with the timed out timer is bypassed so that the devices in the remainder of the loop can continue trying to complete the initialization. The processor initiates a PTBI event on the bypassed device. If the bypassed device is operating properly, it is re-inserted back into the loop.

Abstract: A SES API is disclosed as an interface between SES protocol code and non-SCSI storage enclosure hardware to abstract the SES protocol code from the control of the hardware. To control the hardware, SES commands are sent to the SES protocol code. The SES protocol code is responsive to the SES commands, but has no knowledge of the hardware. The SES protocol code converts the SES command to a series of function calls. When the SES API receives the function calls, it executes the corresponding functions. The SES API includes a customer-tailored interface library of functions. The library allows the end user to provide the hardware interface routines necessary for SES to control the hardware. The functions are written as templates, separate from the SES protocol code, so that end users can modify the functions to control the hardware without having to modify or understand the SES protocol code.

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract: A method and system for allowing flexible control of access to a shared memory by multiple requesters. In a preferred embodiment, the invention arbitrates access to flash memory on a HBA between multiple host channels and HBA microprocessors, and eliminates contention possibilities for the flash during write cycles by the allowing a grant to be locked for a period defined by the flash write protocol and timing.

Abstract: An interrupt notification block stored in host memory is disclosed that contains an image of the interrupt condition contents that may be stored in a host attention register in a host interface port. The interrupt notification block is written by the host interface port and pre-fixed into the port pointer array of a host at the time the host interface port updates the pointers stored in a port pointer array in host memory. The host may then read the interrupt notification block to determine how to process a response or an interrupt rather than having to read the host attention register in the host interface port across the host bus.

Abstract: An apparatus for local direct memory access control includes a processor unit for generating a direct memory access designator when needed data is not available and continuing processing which does not require the unavailable data. A memory access designator holder receives the memory access designator, and a local data memory access controller performs a data memory access transaction in accordance with the content of a descriptor. Staging registers hold components of a data memory access designator and transfer the components to a selected portion of the data memory access designator holder. The data memory access controller transfers the contents of the staging registers to the data memory access designator holder when one of the staging registers is written to by the processor unit.

Abstract: Systems and techniques to track deferred data transfers on a system-interconnect bus. A deferral response initiates storage of information corresponding to the response and tracking of progress for a requested data transfer. A master device, such as a bus adapter, may include a split-transaction repository, timers, and a split-transaction monitor. The master device may include both hardware and firmware components, and may be designed to handle split responses as defined by a Peripheral Component Interconnect Extended standard.

Abstract: A 32-word command IOCB format is disclosed. A conventional 8-word format is supported, although in both cases 32-word command IOCBs are used. When the conventional 8-word format is used, the host sets the LE bit=1 and writes a conventional 8-word command IOCB into words 0-7 of the 32-word command IOCB. The firmware performs a DMA operation and reads the LE bit. With the LE bit=1, the firmware knows to read only words 0-7. When the new 32-word format is used, the host sets the LE bit=0 and writes a 32-word IOCB command into the 32-word command IOCB, including command and response buffer pointers, one or more data buffer pointers, and perhaps the command buffer. The firmware performs a DMA operation and reads the LE bit. With the LE bit=0, the firmware knows to read all 32 words of the command IOCB.

Abstract: A flash configuration space is disclosed for storing configuration data regions. Each configuration data region includes configuration data and a signature tag that identifies the configuration data with various levels of specificity. During a configuration data update, a header in each configuration data region is scanned to see if a valid matching configuration data region already exists. If no valid matching configuration data region exists, the signature tag and configuration data are written into the next available area in the flash configuration space. If a valid matching configuration data region is located, the header and configuration data are written into the next available area in the flash configuration space and the located configuration data region is invalidated.

Abstract: A loop network hub port with an automatic bypass feature. The automatic bypass feature causes the hub port to enter a bypass mode upon detection of a specified loop failure initialization sequence from a node port attached to the hub port. The hub port does not propagate loop failure initialization data generated by the attached node port upon the failure of a data channel from the hub port to the node port. The hub port replaces loop failure initialization data received from the node port with buffer data and conceals the node port failure from the remainder of the loop. Upon detection of the loop failure initialization sequence received from the attached node port, the hub port enters a bypass mode and maintains that bypass mode until a recovery sequence is received from the node port. At that point, the hub port reinserts the node port into the loop.

Abstract: A system, method, software and firmware configured to write a message comprising a plurality of words into a memory, such that a last word of the message is written first at a first memory address and a first word of the message is written last at a memory address higher than the first memory address. The system may comprise two software applications sending messages to each other via a bus, such as a PCI bus.

Abstract: Methods and associated hub arrangements are described for use in diagnosis and recovery in high performance digital loops such as, for example, those seen in Fiber Channel systems. In one system having a hub configured for interconnection of a plurality of stations as part of a digital system such that digital data flows between the stations based on operational status of the system, an arrangement forms part of the hub which arrangement is connectable at points within the hub and between at least two different pairs of the stations for monitoring certain characteristics of the data in a way which provides for non-invasive identification of one or more conditions related to the operational status of the system.