Abstract: Methods and apparatus for switching Fiber Channel Arbitrated Loop Systems is provided between a plurality of Fiber Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

Abstract: Methods and apparatus for switching Fibre Channel Arbitrated Loop Systems is provided between a plurality of Fibre Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

Abstract: The present invention is related to the checking of encryption. Embodiments of the present invention are based on the discovery that sufficiently high reliability may be established without checking every encryption block. Instead, embodiments of the present invention provide that data being encrypted may be sampled at certain rate (which may be constant or varying) and only the sampled data may be checked. In general, embodiments of the present inventions are applicable to a fast encryption circuit that may encrypt an entire stream of incoming data into a stream of encrypted data and one or more slower (or slow) encryption circuit and/or one or more slow decryption circuit that operate(s) only on selected samples of the incoming or encrypted data in order to check the encryption of the fast circuit. Thus, encryption can be verified without incurring the costs of exhaustively checking all encrypted data.

Abstract: A hardware switch for use with hypervisors and blade servers is disclosed. The hardware switch enables switching to occur between different guest OSs running in the same server, or between different servers in a multi-root IOV system, or between different guest OSs running in the same server in single-root IOV systems. Whether embedded in a host bus adapter (HBA), converged network adapter (CNA), network interface card (NIC) or other similar device, the hardware switch can provide fast switching with access to and sharing of at least one external network port such as a Fibre Channel (FC) port, 10 Gigabit Ethernet (10 GbE) port, FC over Ethernet (FCOE) port, or other similar port. The hardware switch can be utilized when no hypervisor is present or when one or more servers have hypervisors, because it allows for switching (e.g. Ethernet switching) between the OSs on a single hypervisor.

Abstract: A 32-word command IOCB format is disclosed. A conventional 8-word format is supported, although in both cases 32-word command IOCBs are used. When the conventional 8-word format is used, the host sets the LE bit=1 and writes a conventional 8-word command IOCB into words 0-7 of the 32-word command IOCB. The firmware performs a DMA operation and reads the LE bit. With the LE bit=1, the firmware knows to read only words 0-7. When the new 32-word format is used, the host sets the LE bit=0 and writes a 32-word IOCB command into the 32-word command IOCB, including command and response buffer pointers, one or more data buffer pointers, and perhaps the command buffer. The firmware performs a DMA operation and reads the LE bit. With the LE bit=0, the firmware knows to read all 32 words of the command IOCB.

Abstract: The buffering of RSCN frames is disclosed so that RSCN traffic can be reduced. At the start of a state change notification period, a timer is started. A state change manager buffers state changes in a register that holds a pending RSCN frame by storing the address of each changed device. When a new state change is received, the address of the corresponding device is compared against each of the addresses currently stored in the buffered RSCN frame. If a duplicate address is found, the searching process ends. If no duplicate address is found, then the new address is added to the next available 32-bit field in the buffered RSCN frame. When a specified number of state changes have been received, or a specified amount of time has elapsed, the RSCN frame is sent to each initiator that had previously registered to receive state changes.

Abstract: Re-sequencing commands and data between a master and slave device utilizing parallel processing is disclosed. When utilizing parallel processing while reading and writing data, there is a chance that the data will be read or written in an improper order, given the time delays associated with different slave devices and the processing time associated with various commands. Therefore, to retain the speed and improved performance of parallel processing while maintaining data coherency, the instructions and data are re-sequenced and processed in the proper order, and the returned data are re-sequenced and returned to the processor in the proper order.

Abstract: Methods and apparatus for switching Fiber Channel Arbitrated Loop Systems is provided between a plurality of Fiber Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

Abstract: Embodiments of the invention are directed to automatically populating a database of names and secrets in an authentication server by sending one or more lists of one or more names and secrets by a network management software to an authentication server. Furthermore, some embodiments provide that the lists being sent are encrypted and/or embedded in otherwise inconspicuous files.

Abstract: The collection of performance data at multiple servers in a SAN and forwarding that data to a centralized server for analysis is disclosed. Remote agents and a central server application collect specific interesting negative event data to enable a picture of the operational health of the SAN to be determined. The agents are placed in servers having HBAs acting as initiators. The agents interact with the HBAs through a driver stack to collect event data. Because of the initiator function they perform, HBAs have visibility to parts of the network that other entities do not have access to, and thus are ideal locations for gathering event data. A SAN diagnostics manager then pulls the collected data from each agent so that a “picture” of the SAN can be developed. In addition to collecting initiator data, the agents also collect errors and performance data from the OS of the servers.

Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: A SES API is disclosed as an interface between SES protocol code and non-SCSI storage enclosure hardware to abstract the SES protocol code from the control of the hardware. To control the hardware, SES commands are sent to the SES protocol code. The SES protocol code is responsive to the SES commands, but has no knowledge of the hardware. The SES protocol code converts the SES command to a series of function calls. When the SES API receives the function calls, it executes the corresponding functions. The SES API includes a customer-tailored interface library of functions. The library allows the end user to provide the hardware interface routines necessary for SES to control the hardware. The functions are written as templates, separate from the SES protocol code, so that end users can modify the functions to control the hardware without having to modify or understand the SES protocol code.

Abstract: A method is disclosed for maintaining a table of recent accesses for each port for use in predicting whether a request for data from a source device is likely to be sent to a high speed or low speed destination device. The table of recent accesses lists every source device attached to that port and the speed of the destination device with the most recent access to each source device. When an OPN primitive is received at the source port, the source device is identified and used with the table of recent accesses to predict whether the destination device is likely to be high speed or low speed, and ultimately whether to send data from the source device or reject the request.

Abstract: A method and apparatus is disclosed for improving the MSI and MSI-X specifications by implementing an efficient delivery and clearing mechanism for interrupt conditions to increase performance between the driver and hardware/firmware interface while ensuring that no interrupts are lost in the process. In particular, an auto clear function is employed to eliminate the need for drivers in the host to send writes over the PCI-based bus to deassert and assert attention enable register bits and clear down attention register bits, and a fail safe mechanism is utilized to prevent lost interrupts.

Abstract: Given the different configurations for SAS and SATA Host and Target Ports, embodiments of the present invention automatically detect the configuration of SATA and SAS Phys when any device is inserted into a port enclosure and properly configure the connection regardless of the Phy configuration of the connected device. When a device is connected to the system, the port listens for either a SATA or SAS OOB signal to determine if the receive pin of the port is properly connected to the transmit signal of the attached device. By switching the configuration periodically and listening for the OOB signal, the port can determine which configuration is proper. Once a signal is detected, the port can properly configure the connection and continue with the SATA or SAS insertion algorithm. A user may alternatively choose which configuration to use and bypass the automatic detection and configuration.

Abstract: Embodiments of the present invention provide for creating and using persistent connections in SAS networks. A persistent connection may be a connection that persists for longer than the usual SAS connection. More specifically, it is a connection that is not subject to periodic tear downs by SAS devices according to existing SAS protocols (such as, by using CLOSE or BREAK primitives). Instead, persistent connections may be removable by a link reset. Persistent connections may be used in situations in which the overhead associated with the usual tear down and re-establishment of connections in a SAS network may be considered too high in comparison with its intended benefits. Persistent connections may also be used to provide virtual direct attachment between two different SAS connected devices or between a SAS connected device and an expander.

Abstract: Snooping in SAS expander networks is disclosed. Ports in a SAS expander may include snoop circuitry and a snoop tap which allows snoop data to be diverted for snooping prior to any significant transformation of the traffic by the regular port logic. Furthermore, the snoop circuitry can receive OOB signaling and convert it to K characters for transmission through the SAS network and subsequent analysis by a protocol analyzer. The ports and cascades in the expander network can be configured to create snoop paths to enable snoop data to be passed through the network to locations where a protocol analyzer can be easily attached. With SAS snoop ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.

Abstract: This is directed to providing Fibre Channel over Ethernet communication. For example a Fibre Channel over Ethernet (FCoE) enabled device (such as a computer) may include a Fibre Channel over Ethernet Adapter (FCoEA). The FCoEA may include an HBA module. The HBA module may be configured to communicate over the Fibre Channel protocol. The FCoE enabled device may process and encapsulate the HBA module's communication in order to send them over an Ethernet network instead. The FCoE enabled device may process communications directed to various Fibre Channel fabric services by utilizing existing Ethernet services, such as an iSNS server. Thus, the FCoE enabled device can emulate a Fibre Channel network for the HBA module using the Ethernet network and one or more Existing Ethernet services/servers.

Abstract: Embodiments of the present invention are directed to enforcing zoning at a network adapter of an end point device. Thus, a network adapter can monitor the communications that are sent and/or received by the adapter and discard communications that are prohibited based on the zoning rules applicable to the adapter. In some embodiments, zoning configuration information can be defined and stored at a central entity and sent to the various network adapters. Alternatively, or in addition, each network adapter can also check outgoing communications to ensure that they include a proper source address. More specifically, outgoing communications may be checked to ensure that their source address is the address (or one of the addresses) that are associated with the network adapter. This can be used to detect and/or prevent malfunctions and/or intentional tampering or hacking.

Abstract: This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.