Abstract: An API in an NPIV-compatible SAN is disclosed that includes functions for creating a vlink, replicating driver software for managing the vlink, monitoring resources in an HBA, or removing a target so that resources can be freed up for other vlinks. The API is part of a driver that communicates with a host OS and also communicates with an HBA to establish the vlinks between the host OS and FC devices. To create vlinks, an “add” function in the API is called by the OS. In addition, when a new vlink is created, a single version of an HBA interface function block is maintained in the driver, but a discovery function block, SCSI bus function block, and I/O function block are all duplicated, forming one logical vlink driver for each vlink. To obtain HBA resource information, a resource monitoring functions in the API may be called by the OS.

Abstract: Systems and techniques to abstract a node discovery process. In general, in one implementation, the technique includes managing node discovery protocols in a network interface device such that a data processing system coupled with the network interface device need not implement the node discovery protocols to effect node discovery. The technique can further include providing the data processing system with block-level storage services and providing an initiator mode and a target mode.

Abstract: Disclosed is a system method and software for user customizable device insertion. A new device is to be inserted in a loop based network such as an FC-AL network. The network is facilitated by a dedicated networking element, such as a switch. In order to ensure that the new device does not adversely affect the network, the new device is tested before it is inserted. Several tests are provided and the user is allowed to choose which tests are to be used. Alternatively, the user is allowed to define his/her own tests. The device is inserted into the network only after it has satisfactorily completed the applicable tests.

Abstract: A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

Abstract: A single SAN management utility is disclosed that discovers all hosts and HBAs in a SAN, configures the storage switches, creates Logical Units within a storage array, and assigns Logical Units to the hosts in the SAN without requiring the administrator to have a detailed understanding of all of the devices in the SAN or a SAN configuration plan. The SAN management utility may first invoke HBA configuration routines to discover and configure the HBAs in the SAN and determine the hosts in which those HBAs reside. The SAN management utility may then utilize the SAN link to set a new IP address for the storage switch, and then configure the switch over an Ethernet connection. In addition, the SAN management utility may interface with a configuration utility in the storage array through a common storage management specification to create and assign Logical Units in the storage array.

Abstract: A method and apparatus is disclosed for improving the MSI and MSI-X specifications by implementing an efficient delivery and clearing mechanism for interrupt conditions to increase performance between the driver and hardware/firmware interface while ensuring that no interrupts are lost in the process. In particular, an auto clear function is employed to eliminate the need for drivers in the host to send writes over the PCI-based bus to deassert and assert attention enable register bits and clear down attention register bits, and a fail safe mechanism is utilized to prevent lost interrupts.

Abstract: An apparatus and method is disclosed for reducing the computational overhead incurred by a host processor during packet processing and improving network performance by adding additional functionality to a Network Interface Controller (NIC). Under certain circumstances the NIC coalesces multiple receive packets into a single coalesced packet stored within a coalesce buffer in host memory. The coalesced packet includes an Ethernet header, a coalesced Internet Protocol (IP) header, a coalesced Transmission Control Protocol (TCP) header, and a coalesced TCP payload containing the TCP payloads of the multiple receive packets. By coalescing received packets into fewer larger coalesced packets within the host memory, the host software needed to process a receive packet will be invoked less often, meaning that less processor overhead is incurred in the host.

Abstract: The synchronization of trunk failover between two FC-AL switches when a primary trunk failure occurs is disclosed. If primary trunk T1 should fail, S1 bypasses the cascade port and sends a MaRK (MRK) ordered set out over duplicate trunk T2 to switch S2. In response, S2 sends an acknowledgement MRK ordered set over T2 back to S1. S1 then reconfigures the switch to establish T2 as the primary trunk, and acts as a masters in the failover process and initiates LIP ordered sets which are communicated to all devices in the system to initialize them. Note that when S2 receives the MRK ordered set and acknowledges it by sending an acknowledgement MRK back to S1, it acts as a slave in the failover process and does not attempt to initiate LIPs, thereby eliminating the possibility of multiple Loop Initialization cycles and reducing the time in which data cannot be transmitted.

Abstract: A system and method are disclosed for enabling the system administrator to identify servers in which the installation of drivers failed without having to examine the installation log of each server by directing the server to send an e-mail to the system administrator in the event of an installation failure. The need for examination of installation logs is eliminated as e-mail messages provide proactive, immediate and specific failure notifications to the system administrator.

Abstract: A blade server is disclosed, comprised of multiple server blades that plug into a midplane from the front, and an I/O router including multiple IOCs (one for each server blade) and an embedded switch that plugs into the midplane from the back. The midplane carries PCI Express lanes for connecting the server blades to the I/O router. Each of the IOCs is physically couplable to a server blade over a separate PCI Express connection in the midplane, preserving existing driver compatibility, and is coupled to the embedded switch via an internal FC link within the I/O router. Each embedded switch may contain full fabric services ports. Alternatively, the full fabric services may be left out, and N_PORT virtualization or FC_AL stealth mode may be employed to allow the embedded switch to interoperate transparently with the external fabric switch and eliminate the third hop in the blade server chassis.

Abstract: A re-programmable finite state machine comprising a content-addressable memory (“CAM”) and a read/write memory output array (“OA”). In operation, the CAM receives and periodically latches a status vector, and generates a match vector as a function of the status vector and a set of stored compare vectors. In response, the OA selects for output one of a set of a control vector as a function of the match vector. A state vector portion of the selected control vector is forwarded to the CAM as a portion of the status vector. An output vector portion of the selected control vector controls the operation of external components. Both the set of stored compare vectors and the set of control vectors are fully re-programmable.

Abstract: Storing frames of data in frame buffers sized to match the frame size when the frame size is not a power-of-two number of bytes is disclosed. The buffer size is chosen to be the largest power-of-two that is less than the frame size. When a frame of data is to be stored, the buffer number of a free buffer is effectively multiplied by the buffer size to obtain a partial frame buffer address Q. The buffer size subtracted from the frame size is referred to as a residual buffer size, and the buffer number is effectively multiplied by the residual buffer size to obtain a residual frame buffer address R. The full frame buffer starting address S=Q+R. For implementations where the difference between the frame size and the buffer size is a power-of-two value, binary shifts and addition can be used instead of a multiplier.

Abstract: A DMA (Direct Memory Access) Exchange Block (DXB) processor may include a receive processor for writing data from a local memory to a host memory over a bus, e.g., a Peripheral Component Interconnect Extended (PCI/X) bus, and a transmit processor for writing data retrieved from the host memory over the bus to the local memory. Each processor may include a high priority queue and a normal priority queue. A controlling program generates DXBs, each of which include a tag assigned by the controlling program and memory descriptors corresponding to a direct memory access operation. The memory descriptor may include a host memory descriptor (address/length) and one or more local memory descriptors. The controlling program writes a DXB to one of the queues in a cache line spill operation. The transfer processor may include two channel registers, enabling the processor to perform two PCI/X data transfers simultaneously.

Abstract: The present invention is directed to providing configuration data to an EEPROM within a sealed enclosure without having to open the enclosure, using a Test Interface Card (TIC) connected to a particular external multi-use port on the enclosure. The present invention is generally applicable to any sealed enclosure containing a device that receives information through an internal serial bus, where the enclosure includes ports that have both high speed, low voltage connections and lower speed DC connections. DC blocking capacitors are placed on the high speed lines, and when a TIC is inserted into the multi-use port, a voltage detection circuit coupled to the high speed connections detects a DC control voltage, tri-states a Switch On a Chip (SOC) and configures switches to connect the lower speed connections to the serial bus and an EEPROM so that the TIC can supply new configuration data to the EEPROM.

Abstract: A system for enabling SATA drives to be utilized in FC SANs is disclosed To send SATA FISs to a SATA drive over a FC SAN, a host sends SCSI commands encapsulated in FC frames over a standard FC link to a Fibre Channel Attached SATA Tunneling (FAST) RAID controller, where the SCSI commands are de-encapsulated from the FC frames and translated to SATA FISs. The SATA FISs are thereafter encapsulated into FC frames. The IOC that performs these functions is referred to as a FAST IOC. The SATA-encapsulated FC frames are sent to multiple disk drive enclosures over another standard FC link. The FC frames are de-encapsulated by FAST switches in disk drive enclosures to retrieve the SATA FISs, and the SATA FISs are sent to the SATA drives over a SATA connection.

Abstract: A method for managing read and write data congestion in a system for executing write and read data commands and having a buffer pool of blocks for temporarily storing read and write data is disclosed. Management of the buffer pool and the initiation of read and write commands ensures that free blocks are available to temporarily store read data arriving at a host bus adapter (HBA). If the currently available blocks would be substantially consumed by the total outstanding inbound read data requested, no more write data commands will be initiated. As inbound read data is received into the buffer pool and subsequently transferred out of the buffer pool to the initiator device, the blocks in the buffer pool are freed up. When the read data transfer is completed and sufficient buffer resources have been freed up, read and write data commands may resume.

Abstract: A system for enabling SATA drives to be utilized in FC SANs is disclosed. To send data to a SATA drive over a FC SAN, a host sends SCSI commands encapsulated in FC frames over a standard FC link to a Fibre Channel Attached SATA Tunneling (FAST) RAID controller, where the SCSI commands are de-encapsulated from the FC frames and translated to SATA FISs. The SATA FISs are thereafter encapsulated into FC frames. The IOC that performs these functions is referred to as a FAST IOC. The SATA-encapsulated FC frames are sent to multiple disk drive enclosures over another standard FC link. The FC frames are de-encapsulated by FAST switches in disk drive enclosures to retrieve the SATA FISs, and the SATA FISs are sent to the SATA drives over a SATA connection.

Abstract: A peripheral component interconnect (PCI) device comprising a bus interface coupled to a component interconnect bus, a plurality of configuration space register sets, and virtual multiple-function logic. Each set of configuration space registers is associated with a function. The virtual multiple-function logic is coupled to the bus interface and the configuration space register sets. The virtual multiple-function logic provides access to a plurality of configuration space registers for a plurality of functions. The virtual multiple-function logic also enables a plurality of functions to share the bus interface and other internal logic.

Abstract: A selectively transparent interface circuit identified herein as a flow-through register (FTR) is disclosed. The FTR enables one or more devices on a primary bus to communicate with a device on a secondary bus without incurring the latency and performance degradation of conventional bridges. The FTR can also provide Hot Swap capability which allows, for example, a device designed for a regular PCI bus to be plugged into a CompactPCI bus while system power remains on. The synchronous flow-through nature of the FTR eliminates the need for large data buffers that would otherwise result in transaction delays and performance degradation. Unlike other types of non-transparent devices such as PCI-to-PCI bridges, the FTR does not occupy any configuration space and is fully transparent to the host and HBA device driver software during flow-through operation, eliminating the need for costly changes to host and device driver firmware/software.

Abstract: A method is disclosed for maintaining a table of recent accesses for each port for use in predicting whether a request for data from a source device is likely to be sent to a high speed or low speed destination device. The table of recent accesses lists every source device attached to that port and the speed of the destination device with the most recent access to each source device. When an OPN primitive is received at the source port, the source device is identified and used with the table of recent accesses to predict whether the destination device is likely to be high speed or low speed, and ultimately whether to send data from the source device or reject the request.