Patents Assigned to Endicott Interconnect Technologies, Inc.
  • Patent number: 8685284
    Abstract: A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: April 1, 2014
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Roy H. Magnuson, Mark D. Poliks, Voya R. Markovich
  • Patent number: 8607445
    Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: December 17, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin
  • Patent number: 8592299
    Abstract: A structure for minimizing resistance between a semi-insulating x-ray detector crystal and an electrically conducting substrate. Electrical contact pads are disposed on the detector crystal and on the substrate with an electrical interconnect between the contact pads formed from a conductive adhesive and washed solder in electrical and mechanical communication with the pads.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: November 26, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Voya R. Markovich, Rabindra N. Das, Rajinder S. Rai, Michael Vincent
  • Patent number: 8558374
    Abstract: An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 15, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Voya R. Markovich, Rabindra N. Das, Frank D. Egitto, James J. McNamara, Jr.
  • Publication number: 20130264669
    Abstract: A method of making a semiconductor radiation detector wherein the metal layers which serve as the cathode and anode electrodes are recessed from the designated prospective dice lines which define the total upper and lower surface areas for each detector such that the dicing blade will not directly engage the metal during dicing and therefore prevent metal from intruding upon (smearing) the vertical side walls of the detector substrate.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Handong Li, Michael Prokesch, John Francis Eger
  • Patent number: 8541687
    Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: September 24, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Voya Markovich, Timothy Antesberger, Frank D. Egitto, William Wilson, Rabindra N. Das
  • Patent number: 8536459
    Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: September 17, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Voya Markovich, Timothy Antesberger, Frank D. Egitto, William Wilson, Rabindra N. Das
  • Patent number: 8499440
    Abstract: A method of making a circuitized substrate including a composite layer having a first dielectric sub-layer including a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: August 6, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papthomas
  • Patent number: 8499445
    Abstract: Printed conductive lines and a method of preparing them using polymer nanocomposites with low resistivity and high current carrying capacity. Plasma treatment selectively removes polymers/organics from nanocomposites. Subsequent selective metal is deposited on top of the exposed metal surface of the printed conductive lines in order to improve current carrying capacity of the conductive printed lines. The printed conductive lines use a conductive ink or printing process and are then cured thermally and/or by a lamination process. Next, the printed conductive lines are treated with the plasma for 5-15 minutes in order to remove organics. E-less copper (Cu) is selectively deposited only at the conducting particle surface of the printed conductive lines. If desired, e-less gold, silver, tin, or tin-lead can be deposited on top of the e-less Cu.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: August 6, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Frank D. Egitto, Voya R. Markovich
  • Patent number: 8502082
    Abstract: A circuitized substrate in which three conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to two dielectric layers. Each of the foil surfaces which physically bond to a respective dielectric layer are smooth (e.g., preferably by chemical processing) and may include a thin, organic layer thereon. One of the conductive layers may function as a ground or voltage (power) plane while the other two may function as signal planes with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: August 6, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, John M. Lauffer
  • Patent number: 8501575
    Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: August 6, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Frank D. Egitto, How T. Lin, John M. Lauffer, Voya R. Markovich
  • Patent number: 8493173
    Abstract: A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: July 23, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Ashwinkumar C. Bhatt, Norman A. Card, Charles Buchter
  • Patent number: 8445094
    Abstract: A circuitized substrate which includes at least one circuit layer and at least one substantially solid dielectric layer comprised of a dielectric composition which includes a cured resin material and a predetermined percentage by weight of particulate fillers, but not including continuous or semi-continuous fibers as part thereof.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: May 21, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert Japp, Kostas Papathomas
  • Patent number: 8446707
    Abstract: A low loss capacitance and low loss insulating dielectric material consisting of a thermosetting resin, thermoplastic resin, a cross-linker, and containing a quantity of ferroelectric ceramic nano-particles of barium titanate within. The combined low loss insulating dielectric layer and a low loss capacitive layer resulting from the material allows one continuous layer that can form internal capacitors and permit the modifying the dielectric thickness between signal layers for impedance matching within a layer of substrate. More significantly, the applied layer of low loss capacitive materials can simultaneously act as a capacitor as well as a dielectric for separation of signal layers.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: May 21, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Konstantinos I. Papathomas, Voya R. Markovich, James J. McNamara
  • Patent number: 8405229
    Abstract: An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: March 26, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Timothy Antesberger, Frank D. Egitto, Voya R. Markovich, William E. Wilson
  • Publication number: 20130033671
    Abstract: A method of conditioning a liquid crystal polymer (LCP) substrate for enhanced surface adhesion accomplished by exposing an LCP substrate to oxygen plasma. The plasma will chemically alter and modify the LCP substrate surface to promote increased adhesion of metal and subsequent LCP layers during lamination. Lamination is accomplished while dwelling under the melt temperature of the LCP substrate itself. A further method is disclosed of detecting impurities modified or deposited onto the LCP surface during plasma treatment.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
    Inventors: Mark Schadt, Frank D. Egitto, Luis J. Matienzo
  • Publication number: 20130033827
    Abstract: A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 7, 2013
    Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
    Inventors: Rabindra N. Das, Voya R. Markovich, John M. Lauffer, Roy H. Magnuson, Konstantinos I. Papathomas, Benson Chan
  • Publication number: 20130025839
    Abstract: An organic substrate capable of providing effective heat transfer through its entire thickness by the use of parallel, linear common thermally conductive openings that extend through the substrate, the substrate having thin dielectric layers bonded together to form an integral substrate structure. The structure is adapted for assisting in providing cooling of high temperature electrical components on one side by effectively transferring heat from the components to a cooling structure positioned on an opposing side. Methods of making the substrate are also provided, as is an electrical assembly including the substrate, component and cooling structure.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 31, 2013
    Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
    Inventors: Frank Egitto, Voya R. Markovich, Varaprasad V. Calmidi, Timothy Antesberger, William E. Wilson
  • Patent number: 8354650
    Abstract: A radiation detection and counting system (2) includes a radiation detector element (5) for outputting a signal related to an energy of a radiation event received thereby and an amplifier (8) for amplifying the signal output by the detector element (5). A gain equalization circuit (10) adjusts the gain of the amplified output signal and a plurality of comparators (12) compare the gain adjusted amplified output signal to a like plurality of different valued threshold signals that are independently adjustable of each other A plurality of counters (20) is operative whereupon only the counter associated with the one comparator (12) that changes state in response to the peak of the gain adjusted amplified output signal exceeding the value of the trigger threshold signal thereof is incremented. A storage (24) stores the incremented value of each counter (20) accumulated over a sample time interval and data output logic circuit (26) transfers the stored accumulated counts out of the storage.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: January 15, 2013
    Assignees: Endicott Interconnect Technologies, Inc., Brookhaven Science Associates, LLC
    Inventors: Joseph Grosholz, Jr., Paul O'Connor, Gianluigi Degeronimo
  • Patent number: 8299371
    Abstract: A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: October 30, 2012
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr.