Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.
Type:
Grant
Filed:
January 20, 2010
Date of Patent:
July 12, 2011
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr., Peter A. Moschak
Abstract: A pinned interposer and mating sockets to facilitate removable mounting of high connection density micro devices between a pair of substrates in compact electronic circuit packages. The pinned interposer has an inner set of contacts, typically in a rectangular array, that, in cooperation with a mating socket, allows pluggable connection of a micro device such as a MEMS device connected to a first printed circuit substrate. An outer set of contacts on the interposer provides electrical interconnection between the first substrate and a second substrate located atop the high connection density micro device, thereby effectively sandwiching the micro device between the first and second substrates. The outer set of contacts may be disposed in a circular array.
Type:
Grant
Filed:
May 28, 2010
Date of Patent:
July 5, 2011
Assignee:
Endicott Interconnect Technologies, Inc.
Abstract: A dielectric composition which is adapted for combining with a supporting material ( e.g., fiber-glass cloth) to form a dielectric layer usable in circuitized such as PCBs, chip carriers and the like. As such a layer, it includes a resin, a predetermined percentage by weight of a filler, and, significantly, only a minor amount of bromine. A circuitized substrate comprised of one or more of these dielectric layers and one or more conductive layers is also provided.
Type:
Grant
Filed:
November 3, 2005
Date of Patent:
April 26, 2011
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas
Abstract: A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.
Type:
Grant
Filed:
March 30, 2007
Date of Patent:
March 22, 2011
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Norman A. Card, Robert J. Harendza, John J. Konrad, Tonya L. Mosher, Susan Pitely, Jose A. Rios
Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.
Type:
Grant
Filed:
May 23, 2006
Date of Patent:
March 1, 2011
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
Abstract: A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.
Type:
Grant
Filed:
January 24, 2008
Date of Patent:
January 25, 2011
Assignee:
Endicott Interconnect Technologies, Inc.
Abstract: A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.
Type:
Grant
Filed:
May 2, 2007
Date of Patent:
January 18, 2011
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Rabindra N. Das, John M. Lauffer, Vova R. Markovich
Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.
Type:
Application
Filed:
August 11, 2010
Publication date:
December 30, 2010
Applicant:
ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Inventors:
John M. Lauffer, Voya R. Markovich, Michael Wozniak
Abstract: A pinned interposer and mating sockets to facilitate removable mounting of high connection density micro devices between a pair of substrates in compact electronic circuit packages. The pinned interposer has an inner set of contacts, typically in a rectangular array, that, in cooperation with a mating socket, allows pluggable connection of a micro device such as a MEMS device connected to a first printed circuit substrate. An outer set of contacts on the interposer provides electrical interconnection between the first substrate and a second substrate located atop the high connection density micro device, thereby effectively sandwiching the micro device between the first and second substrates. The outer set of contacts may be disposed in a circular array.
Type:
Application
Filed:
May 28, 2010
Publication date:
December 23, 2010
Applicant:
ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Abstract: A flexible circuit electronic package including a heat sink, a flexible circuit having a semiconductor chip positioned thereon and electrically coupled thereto, and a quantity of heat shrunk adhesive securing the flexible circuit to the heat sink such that the flexible circuit is planar. This package is then adapted for being positioned on and electrically coupled to a circuitized substrate such as a printed circuit board. A method of making this package is also provided.
Type:
Grant
Filed:
March 26, 2007
Date of Patent:
December 14, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Abstract: An LED lighting assembly including a plurality of individual LEDs mounted on a common, bendable heat sinking member designed to remove heat from the LEDs during operation and also to be formed (bent) to provide the desired light direction and intensity. Several such assemblies may be used within an LED lamp, as also provided herein. The lamp is ideal for use within medical and dental environments to assure optimal light onto a patient located at a specified distance from the lamp.
Type:
Grant
Filed:
April 2, 2007
Date of Patent:
November 30, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Benson Chan, John E. Kozol, John M. Lauffer, How T. Lin
Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.
Type:
Grant
Filed:
April 17, 2008
Date of Patent:
November 23, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
John M. Lauffer, Voya R. Markovich, Michael Wozniak
Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.
Type:
Grant
Filed:
April 21, 2005
Date of Patent:
November 9, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr., Peter A. Moschak
Abstract: A method of making a multilayered circuitized substrate assembly which includes bonding at least two circuitized substrates each including at least one layer of high temperature dielectric material, one of these layers in turn including at least one thru-hole therein having therein a quantity of a a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered during the bonding to form a conductive path through the dielectric of one of the substrates.
Type:
Grant
Filed:
September 28, 2007
Date of Patent:
November 2, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Frank D. Egitto, Voya R. Markovich, Luis J. Matienzo
Abstract: A method of making a circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer.
Type:
Grant
Filed:
July 10, 2006
Date of Patent:
October 19, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
John M. Lauffer, James M. Larnerd, Voya R. Markovich
Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.
Type:
Grant
Filed:
March 2, 2009
Date of Patent:
September 28, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
Abstract: A system and method for identifying and controlling the movement of various items, e.g., suitcases, associated with respective ones of various individuals, e.g., those desiring to travel on a selected means of transportation such as an airline, railway or the like. The system includes a plurality of programmable fingerprint readers each associated with a respective one of the items, a fingerprint scanner for scanning fingerprints from each individual and associating it with one or more of the items, a CPU for receiving readings from each of the item fingerprint readers and information from the scanner, and a retrieving unit (e.g., such as one owned by the transporting party) which retrieves selected ones of the fingerprint readings stored by the CPU for comparing with also retrieved readings from the respective fingerprint readers when the traveling individual presents an item to the transporting party for travel.
Type:
Grant
Filed:
December 22, 2003
Date of Patent:
September 21, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Ashwinkumar Bhatt, Michael Hills, James J. McNamara, Jr., Candido Tiberia
Abstract: A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.
Type:
Grant
Filed:
April 9, 2007
Date of Patent:
September 21, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Kim J. Blackwell, Frank D. Egitto, John M. Lauffer, Voya R. Markovich
Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.
Type:
Grant
Filed:
September 9, 2008
Date of Patent:
September 7, 2010
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Rabindra N. Das, John M. Lauffer, Irving Memis, Steven G. Rosser
Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.
Type:
Application
Filed:
March 10, 2010
Publication date:
July 1, 2010
Applicant:
ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Inventors:
Rabindra N. Das, John M. Lauffer, Irving Memis, Steven G. Rosser