Patents Assigned to ENGINEER INC.
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Publication number: 20220037244Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.Type: ApplicationFiled: August 3, 2020Publication date: February 3, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Li-Hua TAI, Wen-Pin HUANG
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Publication number: 20220037290Abstract: A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.Type: ApplicationFiled: October 12, 2021Publication date: February 3, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stefan ESSIG
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Publication number: 20220037242Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are substantially arranged in a row and spaced apart from one another. The conductive through via extends through the dam portions.Type: ApplicationFiled: July 31, 2020Publication date: February 3, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wen Hung HUANG, Min Lung HUANG
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Patent number: 11236713Abstract: A sealed intake air system incorporates a positive connection seal interface between the air filter and the airbox with captive fasteners to provide a positive connection between the air filter and the one-piece airbox.Type: GrantFiled: July 12, 2019Date of Patent: February 1, 2022Assignee: Advanced Flow Engineering, Inc.Inventors: Shahriar Nick Niakan, George R. Chiang
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Publication number: 20220028596Abstract: An inductor unit includes a conductive structure, a first magnetic element and an insulating layer. The conductive structure has a bottom conductive layer, a top conductive layer, and a first side conductive layer extending from the bottom conductive layer to the top conductive layer. The first magnetic element is disposed on the bottom conductive layer of the conductive structure. The insulating layer is disposed on the bottom conductive layer of the conductive structure, wherein the insulating layer covers and surrounds the first magnetic element. The circuit structure including the inductor unit and the methods for manufacturing the same are also provided.Type: ApplicationFiled: July 23, 2020Publication date: January 27, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Huang-Hsien CHANG, Yunghsun CHEN
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Publication number: 20220028800Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a die and a stiffener. The substrate has an upper surface. The die is disposed on the upper surface of the substrate. The stiffener is disposed on the upper surface of the substrate and surrounds the die. The stiffener has a first upper surface adjacent to the die, a second upper surface far from the die and a lateral surface extending from the first upper surface to the second upper surface. A first distance between the first upper surface of the stiffener and the upper surface of the substrate is less than a second distance between the second upper surface of the stiffener and the upper surface of the substrate.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jui-Tzu CHEN, Yu-Hsing LIN, Chia-Chieh HU, Chun-Cheng KUO, Yu-Hsiang CHAO
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Publication number: 20220028836Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the first surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.Type: ApplicationFiled: October 4, 2021Publication date: January 27, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shang-Ruei WU, Chien-Yuan TSENG, Meng-Jen WANG, Chen-Tsung CHANG, Chih-Fang WANG, Cheng-Han LI, Chien-Hao CHEN, An-Chi TSAO, Per-Ju CHAO
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Publication number: 20220028801Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsing Kuo TIEN, Chih-Cheng LEE
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Publication number: 20220026933Abstract: An apparatus and methods are provided for a portable mass airflow (MAF) training module configured to simulate an air intake into an internal combustion engine. An in-line blower draws an airflow through an air filter by way of a first air duct and a second air duct. A throttle assembly is coupled between the first air duct and the second air duct. The throttle assembly includes a throttle plate that may be rotated to regulate the airflow. The power output of the in-line blower is variable to simulate the air intake of various sizes of the internal combustion engine. A MAF sensor and a duct velocity sensor are configured to provide airflow information. The portable MAF training module enables a practitioner to select a desired throttle setting and observe a resultant mass airflow through the portable MAF training module that is measured by the MAF sensor.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Applicant: K&N Engineering, Inc.Inventors: Mac McClanahan, Steve Williams, Joel Valles
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Publication number: 20220028817Abstract: At least some embodiments of the present disclosure relate to a method for manufacturing a bonding structure. The method includes: providing a substrate with a seed layer; forming a conductive pattern on the seed layer; forming a dielectric layer on the substrate and the conductive pattern; and removing a portion of the dielectric layer to expose an upper surface of the conductive pattern without consuming the seed layer.Type: ApplicationFiled: July 23, 2020Publication date: January 27, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG
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Patent number: 11229823Abstract: A maximum push-up exercise machine for various push-up exercises in the prone position on a platform with added resistance. An embodiment of the device includes a cable-pulley weight stack system housing with a cable-pulley weight stack system that is welded, bolted, or connected in any manner to the platform. The configuration of the cable-pulley weight stack system may be in any manner such that a cable thimble is positioned midpoint of the platform. The cable thimble is configured to connect to receive a snap link hook suspended from a harness or belt worn by a user, connect to a single cable handle attachment, and connect to a push-up bar via a push-up bar cable connector.Type: GrantFiled: November 4, 2020Date of Patent: January 25, 2022Assignee: OK Engineering Inc.Inventors: Omar Ismail KashKash, Yousef Ismail KashKash
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Publication number: 20220020605Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a conductive base, a first semiconductor die, a first conductive pillar, and a first encapsulant. The conductive base has a first surface. The first semiconductor die is disposed on the first surface of the conductive base. The first conductive pillar is disposed on the first semiconductor die. The first encapsulant is disposed on the first surface of the conductive base. The first encapsulant encapsulates the first semiconductor die. The first encapsulant includes an opening defined by the first conductive pillar.Type: ApplicationFiled: July 20, 2020Publication date: January 20, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kay Stefan ESSIG, Jean Marc YANNOU, Bradford FACTOR
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Publication number: 20220020885Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.Type: ApplicationFiled: September 28, 2021Publication date: January 20, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Pin TSAI, Tsung-Yueh TSAI, Teck-Chong LEE
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Publication number: 20220021250Abstract: A variable reluctance stepper motor comprises a stator and a rotor that is rotatable relative to the stator. The stator comprises an annular outer yoke with a set of circumferentially spaced stator poles at equal angular intervals around the yoke extending radially inward from first portions of the yoke toward the rotor. Phase windings are individually coiled around each of the respective stator poles. Multiple slots are formed in an outer perimeter edge of the yoke at second portions thereof circumferentially situated between the first portions. A permanent magnet is embedded within each slot with circumferentially directed magnetic orientation of the respective permanent magnets. The remote placement of the magnets ensure that detent torque is kept to a minimum, while also increasing holding and dynamic torque levels.Type: ApplicationFiled: December 3, 2020Publication date: January 20, 2022Applicant: Lin Engineering, Inc.Inventors: Ted T. Lin, JianJun Gan
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LEAD FRAME, PACKAGE STRUCTURE COMPRISING THE SAME AND METHOD FOR MANUFACTURING THE PACKAGE STRUCTURE
Publication number: 20220020680Abstract: A lead frame includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion and an outer lead portion connecting to the inner lead portion. The inner lead portion is adjacent to and spaced apart from the die paddle. A bottom surface of the inner lead portion is higher than a bottom surface of the outer lead portion. The bottom surface of the inner lead portion includes one or more supporting members disposed thereon. The one or more supporting members have a convex surface facing away from the inner lead portion.Type: ApplicationFiled: July 14, 2020Publication date: January 20, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chia Hsiu HUANG, Chun Chen CHEN, Wei Chih CHO, Shao-Lun YANG, Yu-Shun HSIEH -
Publication number: 20220020674Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers and a plurality of circuit layers in contact with the dielectric layers. The conductive through via extends through the conductive structure. The conductive through via is a monolithic structure, and includes a main portion and an extending portion protruding from the main portion.Type: ApplicationFiled: July 16, 2020Publication date: January 20, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Wen Hung HUANG
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Publication number: 20220020654Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a first substrate, a second substrate, and a barrier structure. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface facing the second surface of the first substrate. The first substrate electrically bonds to the second substrate through a conductive terminal disposed between the second surface of the first substrate and the first surface of the second substrate. The barrier structure is disposed adjacent to the first surface of the first substrate.Type: ApplicationFiled: July 20, 2020Publication date: January 20, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei Chih CHO, Chun Chen CHEN, Shao-Lun YANG
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Patent number: 11225932Abstract: An apparatus and method are provided for a fuel bowl to supply liquid fuel to a carburetor. The fuel bowl comprises a float chamber and a fuel inlet cavity which receives a fuel delivery insert. The fuel delivery insert receives a fuel inlet valve and comprises passages to direct incoming fuel to a bottom portion of the float chamber. A float comprises an elongate member rotatably hinged within a float cavity of the fuel delivery insert, such that the float rises according to a quantity of fuel within the float chamber. The fuel inlet valve supplies liquid fuel to the float chamber by way of the passages according to the operation of the float within the float chamber. A ventilation chamber allows air and fuel vapors to exit as liquid fuel enters the float chamber while preventing liquid fuel from entering into the carburetor.Type: GrantFiled: April 3, 2020Date of Patent: January 18, 2022Assignee: K&N Engineering, Inc.Inventor: John Kyle
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Publication number: 20220013443Abstract: A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Chang-Lin YEH
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Patent number: D941253Type: GrantFiled: July 3, 2018Date of Patent: January 18, 2022Assignee: WirthCo Engineering, Inc.Inventors: Andrew W. Wirth, Kelly T. Eagan