Patents Assigned to Engineering
  • Patent number: 7042078
    Abstract: A semiconductor package includes spacers, a chip, bonding wires, contacts, and an encapsulant. The chip is disposed on the spacers. The bonding wires are electrically connected to the chip, and the contacts are electrically connected to the bonding wires. The contacts are electrically connected to an external circuit board. The encapsulant encapsulates the spacers and the active and back surfaces of the chip so as to lower the thermal stress of the chip.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: May 9, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Jeng Da Wu
  • Patent number: 7042143
    Abstract: In piezoceramic multilayer actuators, the head region and the foot region consist of inactive, that is to say electrode-free, piezoceramic layers. Due to the arrangement of the metallic electrodes and the layers of the piezoceramic materials, the shrinkage of the piezoceramic material, in particular in the passive head region and foot region, is influenced during the sintering process and can cause the formation of cracks. Different expansion behavior of the active and of the passive region during operation also lead to stresses which favor crack formation, in particular at the boundary between both regions. According to the invention, it is therefore proposed that a transition region (11), whose shrinkage and expansion behavior lies between the shrinkage and expansion behavior of the active region (10) and the shrinkage and expansion behavior of an inactive region (8, 9) which are electrode free, adjoins the active region (10) up to the inactive head region (8) and up to the inactive foot region (9).
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: May 9, 2006
    Assignee: CeramTec Ag Innovative Ceramic Engineering
    Inventors: Reiner Bindig, Jürgen Schmidt, Matthias Simmerl, Günter Helke, Hans-Jürgen Schreiner
  • Patent number: 7040132
    Abstract: The two-piece upper work tool 20 includes a first body member 22 and a second body member 24 which are generally mirror images of each other. The body members 22, 24 include a plurality of orifices 28 therethrough. One of the body members 22 includes a plurality of elongated slots 26 with a circular shape at one end thereof. The other body member 24 has a plurality of fasteners, posts or dowels 30 extending from a surface thereof which interact and mate with the elongated slots 26 on the opposite body member 22. The body members 22, 24 include a rectangular shaped recess 32 on one end thereof and also include a plurality of pockets or cavities on inner surfaces thereof. One of the pockets includes a diameter for a back-up roller generally encompassing 360° except for a very small top portion thereof.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: May 9, 2006
    Assignee: Lonero Engineering Company, Inc.
    Inventor: Vincent J. Lonero
  • Patent number: 7043408
    Abstract: A universal CAD-neutral data management system capable of two-way exchange of information between a CAD-neutral database and any one of a variety of proprietary CAD graphics platforms. An updateable CAD-neutral database includes parameter descriptions arrayed against parameter values and may further include parameter type information.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: May 9, 2006
    Assignee: Virtual Supply Chain Engineering, Inc.
    Inventors: Jeffrey Camiener, David Kassel, Michael McCoy
  • Patent number: 7040128
    Abstract: A method and device for checking clearance between a stamping die includes a template representative of relative movement between the stamping die and end tool. A template including a surface representing movement of the end tool relative to the stamping die is positioned relative to the stamping die. The position is indicative of a location of the end tool during operation of the stamping die. Contact between the template and the stamping die along the surface representing movement indicates potential contact between the end tool and the stamping die during operation.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: May 9, 2006
    Assignee: Syron Engineering & Manufacturing, LLC
    Inventors: Scott McCallum, Paul Kleine, Rick Hurst
  • Patent number: 7042430
    Abstract: A liquid crystal display device has a liquid crystal display panel and a drive circuit for supplying gray scale voltages to pixels in the liquid crystal display panel. The drive circuit selects desired gray scale voltage levels from a gray scale voltage varying with time in a staircase fashion, in accordance with display data, and supplies the selected gray scale voltage levels to the pixels. The drive circuit includes a stabilizer circuit provided to a gray scale voltage line for supplying the gray scale voltage varying with time.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: May 9, 2006
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hironobu Isami, Iwao Takemoto, Katsumi Matsumoto
  • Publication number: 20060091332
    Abstract: Conventionally, a particle/defect inspection apparatus outputs a total number of detected particles/defects as the result of detection. For taking countermeasures to failures in manufacturing processes, the particles/defects detected by the inspection apparatus are analyzed. Since the inspection apparatus outputs a large number of detected particles/defects, an immense time is required for analyzing the detected particles/defects, resulting in a delay in taking countermeasures to a failure in the manufacturing processes. In the present invention, an apparatus for optically inspecting particles or defects relates a particle or defect size to a cause of failure in an inspection result. A data processing circuit points out a cause of failure from the statistics on the inspection result, and displays information on the inspection result.
    Type: Application
    Filed: December 13, 2005
    Publication date: May 4, 2006
    Applicants: Hitachi High-Technologies Corporation, Hitachi, Ltd., Hitachi Electronics Engineering Co., Ltd.
    Inventors: Hidetoshi Nishiyama, Minori Noguchi, Yoshimasa Ooshima, Akira Hamamatsu, Kenji Watanabe, Tetsuya Watanabe, Takahiro Jingu
  • Publication number: 20060094223
    Abstract: A wafer fabricating method at least includes the steps of providing a wafer having an active surface with a plurality of pads, forming a plurality of bumps on the pad, and forming an organic protective layer on the bump and the active surface. Besides improving the quality of the wafer, the wafer structure according to the invention is oxidation-resistant, thus avoiding the cold-joint problem when soldered to the substrate.
    Type: Application
    Filed: July 19, 2005
    Publication date: May 4, 2006
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chi-Long Tsai
  • Publication number: 20060094226
    Abstract: A bumping process is provided as following: at first, providing a wafer, then forming a first photo-resist layer on a active surface of the wafer and forming at least a first opening on the first photo-resist layer; and forming a copper pillar in the first opening; then forming a second photo-resist layer on the first photo-resist layer and forming at least a second opening on the second photo-resist layer; finally forming a solder layer in the second opening to attach the solder layer on the copper pillar, and removing the first and second photo-resist layer.
    Type: Application
    Filed: September 20, 2005
    Publication date: May 4, 2006
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Lung Huang, Yi-Hsin Chen, Jia-Bin Chen
  • Publication number: 20060091528
    Abstract: A high heat dissipation flip chip package structure including a substrate, a chip, a supporting structure, and a heat spreader is provided. The substrate has a substrate surface. The chip has an active surface with several bumps formed thereon. The bumps are connected to the substrate surface. The supporting structure has an upper part having a first opening and a lower part fixed on the substrate surface. The first opening corresponds to the chip. The heat spreader having at least a second opening is fixed on the upper part. The first opening is connected to outside through the second opening. The heat generated by the chip is not only dissipated to outside through the heat spreader by the heat conduction, but also dissipated to outside by the heat convection at the first opening and the second opening.
    Type: Application
    Filed: July 18, 2005
    Publication date: May 4, 2006
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Ching-Hsu Yang
  • Publication number: 20060091384
    Abstract: A substrate testing apparatus with full contact configuration. The apparatus includes a jig and a full-contact probe substrate. The jig has a conductive tape disposed thereon for fully electrically connecting a plurality of first connecting pads disposed on an upper surface of a substrate strip. The full-contact probe substrate has a contact surface and includes a plurality of conductive bumps and contact pads. The conductive bumps are disposed on the contact surface, and are used for individually probing a plurality of corresponding second connecting pads disposed on a lower surface of the substrate strip. The contact pads are electrically connected to the conductive bumps. The substrate strip is fully tested by means of the jig and the full-contact probe substrate.
    Type: Application
    Filed: October 17, 2005
    Publication date: May 4, 2006
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung-Hsiung Ho, Jui-Wen Wang, Tien-Ming Shih, Kuang-Lin Lo
  • Publication number: 20060094161
    Abstract: A thermal enhance package mainly comprises a chip, a substrate unit, a heat spreader unit and a plurality of pellets. The chip is disposed above the substrate unit and electrically connected to the substrate unit, and an encapsulation unit encapsulates the chip, the substrate unit, the heat spreader unit and the pellets. Therein the pellets are formed on the substrate unit and connect the substrate unit and the heat spreader unit. Thus the heat arisen out of the chip can be transmitted to the heat spreader unit not only through the encapsulation unit but also the pellets. Moreover, the substrate unit has at least one grounding contact connecting to one of the pellets so as to provide the thermal enhance package a good shielding. In addition, a method for manufacturing the thermal enhance package is also provided.
    Type: Application
    Filed: December 16, 2005
    Publication date: May 4, 2006
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Su Tao
  • Publication number: 20060093696
    Abstract: A device for the preparation of plastics material, in particular thermoplastic plastics material, has a receiving container (1) for the material, the interior of the said receiving container (1) having tools (21) provided therein which are arranged on a carrier disc (9). The tools are driven by a shaft (4) for rotation about the, in particular vertical, axis (8) of the shaft (4). At least one screw (17) is provided for the removal of the material out of the receiving container (1). The screw housing (16) has a feed opening (27) which is connected with respect to flow to a discharge opening (15) in the container (1), which discharge opening (15) is situated at a lower level than the carrier disc (9) and the tools (21) carried by it. Further moved tools (12), which convey the material into the discharge opening (15), are provided in the receiving container (1) below the carrier disc (9).
    Type: Application
    Filed: February 2, 2005
    Publication date: May 4, 2006
    Applicant: Erema Engineering Recycling Maschinen und Anlagen Gesellschaft m.b.H.
    Inventors: Helmut Bacher, Helmuth Schulz, Georg Wendelin, Klaus Feichtinger
  • Publication number: 20060094224
    Abstract: A bumping process is provided. The bumping process comprises the steps of: firstly, providing a wafer; next forming an under bump metallurgy (UBM) on the active surface of the wafer; then, forming a photo-resist layer on the active surface of the wafer and forming at least an opening in the photo-resist layer; then, sequentially forming a copper post, a barrier and a copper layer; then removing the photo-resist layer; finally reflowing the solder layer in the opening. The barrier layer is made of the materials such as nickel, lest the copper post and the solder layer might contact directly, causing the copper to diffuse fast and lose accordingly. Therefore, the quality of bumping process and structure can be enhanced according to the present invention.
    Type: Application
    Filed: October 18, 2005
    Publication date: May 4, 2006
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Lung Huang, Yi-Hsin Chen, Jia-Bin Chen
  • Patent number: 7037093
    Abstract: A dividing device, comprising at least one vane-type rotor comprising a hub provided with continuous vanes which are slidable through the hub along their longitudinal axis and almost perpendicular to the axis of the hub, the hub being provided with axial grooves for holding the continuous vanes which grooves partially divide the hub in sections, a part of the sections being provided with an aperture axially through the hub, for providing a means for connecting several vane-type rotors to each other, the apertures being unround.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: May 2, 2006
    Assignee: De Jong Engineering Elburg B.V.
    Inventor: Pieter De Jong
  • Patent number: 7036774
    Abstract: A train control system includes a control module that determines a position of a train using a positioning system and consults a database to determine when the train is approaching a portion of track monitored by a track circuit. When the train is near a track circuit, but while the train is still far enough away from the track circuit such that the train can be stopped before reaching the portion of track monitored by the track circuit, the train transmits an interrogation message to a transceiver associated with the track circuit. When the track circuit receives the interrogation message, a test is initiated. The test results are transmitted back to the train. The train takes corrective action if the track circuit fails to respond or indicates a problem.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: May 2, 2006
    Assignee: Quantum Engineering, Inc.
    Inventors: Mark Edward Kane, James Francis Shockley, Harrison Thomas Hickenlooper
  • Patent number: 7037040
    Abstract: A method for the placement of subterranean electrodes is disclosed and which includes the steps of providing an earth engaging drill; forming a bore hole in the surface of the earth with the earth engaging drill; providing an electrode; and delivering the electrode into the bore hole by employing the earth engaging drill.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: May 2, 2006
    Assignee: Applied Geotechnical Engineering and Construction, Inc. (Agec, Inc.)
    Inventors: Steven J. Phillips, Robert G. Alexander
  • Patent number: 7038357
    Abstract: A transducer is designed and fabricated using stretched rolled electroactive polymers. The invention includes the design, fabrication, and integration of a stretched rolled actuator system with corresponding sensing, control and power subsystems. The invention presented is based on the improved performance of electroactive polymer transducers that can be achieve by prestretching the polymeric material. In this invention, the preferred stretch is maintained in a rolled configuration by introducing structural elements to the transducer. The structural elements facilitate fabrication of the transducer as well as provide a compact and efficient means of maintaining stretch and the desired boundary conditions on the electroactive polymer during operation. These conditions together are used to improve and tailor the strain response of the transducer.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: May 2, 2006
    Assignee: Engineering Services Inc.
    Inventors: Andrew A. Goldenberg, Landy Toth, Alex Kapps
  • Patent number: 7036663
    Abstract: A package of a roll, particularly a paper web roll comprising a wrapper, particularly a paper web wrapper wound stagewise into at least two wrappings about the roll in an overlap fashion. The paper web wrapper is wound about the roll in a slightly helical manner so that the edges of the wrapper layers overlap in a staggered fashion. The staggered edges of the overlap wrapping are formed so that each superposed wrapper layer conceals the underlying wrapper layer, whereby in a finished wrapping of a product only one wrapper edge remains visible.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: May 2, 2006
    Assignee: Saimtec Engineering Oy
    Inventors: Ismo Itkonen, Tapio Korhonen, Risto Laukkanen, Esa Nuutinen, Juha Pitkänen, Heikki Rasimus, Seppo Rasimus, Timo Silvennoinen, Veli Ulvinen
  • Patent number: 7037750
    Abstract: A method of manufacturing a package is disclosed. The manufacturing method includes the steps of providing a substrate having an opening, disposing a metal slice on a bottom surface of the substrate to cover the opening and bond pads on the bottom surface of the substrate, disposing a die on the metal slice inside the opening or above the top surface of the substrate outside the opening, forming a number of bond wires between the top surface of the die and the top surface of the substrate to electrically connect the die to the substrate, forming an encapsulating mold compound to cover the die, the bond wires, and a part of the top surface of the substrate, removing a part of the metal slice to form a metal heat slug thermally connected to the die and to expose the bond pads, and forming a number of solder balls on the exposed bond pads.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: May 2, 2006
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Yu-Fang Tsai, Chin-Hsien Lin, Tsung-Yueh Tsai