Abstract: Systems and methods for reducing the amount of power consumed by an electronic or electrical device by using collected knowledge of the operation of the device to determine when to place the device in an ultra-low power consumption mode.

Abstract: A system includes a first circuit and a second circuit. The first circuit includes a first MOS transistor having a gate and a drain. The first circuit is configured to receive a radio frequency (RF) signal at the gate of the first MOS transistor. The drain of the first MOS transistor is configured to output a first current that is proportional to the square of the input voltage of the RF signal while receiving the RF signal. The second circuit includes a second MOS transistor having a source configured to receive a first current from the first circuit. The second MOS transistor is biased in a triode region and has a channel resistance between the source and a drain. The second circuit is configured to output a voltage proportional to the value of the power of the RF signal received by the first circuit.

Abstract: The present invention provides a system and method for protecting data stored in the control registers of an integrated circuit, such as a television chip. The system and method use one or more selectively activated read protection modules to prevent the control registers from being read unless a predetermined key or password is entered. The password or key may be stored in password registers within the chip. A key access generator will enable read access of the control registers if correct values are written to the appropriate password registers. The key access generator may enable read access for a predetermined period of time or until it receives another input.

Abstract: Systems and methods for scheduling network communications in a managed network can include a Network Controller discovering a plurality of network nodes; the Network Controller classifying the discovered network nodes into two or more classifications of node for node-level prioritization of network communications; the Network Controller receiving reservation requests from at least some of the plurality of network nodes, wherein the reservation requests request one or more time slots for their respective network nodes in an upcoming communication window; and the Network Controller assigning time slots in the upcoming communication window to one or more network nodes in response to reservation requests, wherein the assignment is based on a priority of the network nodes and wherein the priority is assigned to the nodes according to their classification.

Abstract: The present application relates to a method for frame rate conversion. The present application relates also to a system for frame rate conversion and a computer comprising said frame rate. In addition, the present application relates to a computer readable medium having a computer program for performing said method. The method comprises defining a first frame rate profile with a first frame rate, defining at least a second frame rate profile with a second frame rate, rendering video frames at the first frame rate profile, detecting the quality of the rendered video frames, and switching from the first frame rate profile to the second frame rate profile at least depending on the detected quality of the rendered video frames.

Abstract: An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.

Abstract: Systems and methods for controlling a power amplifier includes combining a digital modulated data signal with a digital bias signal to generate a combined digital signal, the digital bias signal generated based on an envelope for the modulated data signal; converting, by a digital-to-analog converter, the combined digital signal into a combined analog signal, the combined analog signal comprising an analog modulated data signal and an analog envelope bias signal; and separating the analog modulated data signal and the analog bias signal onto separate signal paths, wherein the converting is performed using a single digital-to-analog converter.

Abstract: Techniques to reduce the transmission overheads in a communication system are disclosed. In an embodiment, a method described herein relates to the elimination of redundant padding to realize an integer number of FEC code-words during the FEC-encoding process of transmission as well as the reduction/elimination of redundant padding to realize an integer number of transmission symbols during the subcarrier modulation mapping process of transmitting OFDM/ACMT/DMT symbols. The techniques are described in the context of a communication system based on the MoCA specification. Furthermore, techniques for channel-profiling, channel-estimation and bandwidth request/grant signaling that facilitate the realization of the method of reduction of transmission overheads in a MoCA system are also described.

Abstract: An LDPC parity check matrix includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of two or more columns of the parity portion are the same.

Abstract: Systems and methods for establishing Parameterized QoS flows in a managed network can include a Designated Network Node (like a Network Controller or any network node) discovering a plurality of network nodes.

Abstract: Various embodiments of methods and systems for pausing and shaping data flow while supporting both parameterized and prioritized Quality of Service are disclosed. In some embodiments, a system for pausing and shaping data flow comprises an input buffer, a first pause controller coupled to the input buffer and an output buffer for flow control messages. Various embodiments also include a hop-1 buffer coupled to the input buffer and a hop-2 buffer comprising a plurality of queues coupled to the hop-1 buffer. Additionally, in some embodiments, a second pause controller is coupled to the queues. The second pause controller selects a queue or queues that will cause a pause to be generated based on a predetermined condition. A two-hop process controller controls the data packet flow from the input buffer to the hop-1 buffer and from the hop-1 buffer to the hop-2 queues based on packet classification.

Abstract: Methods and systems for digitization of broadband analog signals may comprise in a radio frequency (RF) transceiver comprising a diplexer, first and second automatic gain and slope control (ASCS) modules, a combiner, and an analog to digital converter (ADC): receiving an input RF signal comprising at least two signals, splitting the input RF signal in the frequency domain into first and second signals of different frequency utilizing the diplexer, configuring a frequency-dependent gain level for each of the first and second signals utilizing the first and second ASCS modules, combining output signals from the first and second ASCS modules utilizing the combiner, and converting the combined output signals to a digital signal utilizing the ADC. The frequency dependent gain levels of the first and second signals may be configured to enable the ADC to operate with an effective number of bits (ENOB) of approximately 10.

Abstract: Systems and methods for dynamically adjusting the gain in a receiver front end to have a desired amount of headroom, based upon a measurement of the signal to noise ratio (SNR) of the output of a digital to analog converter and the amount of degradation to the SNR due to previous adjustments to the gain.

Abstract: Systems and methods for canceling cross-coupled satellite signals in a LNB IC include receiving a first satellite signal at a first input of the LNB IC and filtering the first satellite signal using a first adaptive filter, the first adaptive filter having first filter coefficients; combining the adjusted first satellite signal with a second satellite signal received at a second input of the LNB IC to generate a first combined satellite signal; measuring the total output power of the combined satellite signal; changing the filter coefficients of the first adaptive filter; remeasuring the total output power of the first combined satellite signal after the changing of the first filter coefficients to determine whether the total power of the first combined satellite signal has decreased.

Abstract: The use of traffic flag symbols allows a large number of CPEs to transmit traffic notifications to a network controller. In some such embodiments, hundreds of CPEs simultaneously transmit traffic flags on different subcarriers of a channel. For example, in a MoCA2 based access network, up to 480 CPEs can transmit flags in only 5 ?s in the 100 MHz-wide channel.

Abstract: A progressive JPEG bitstream may comprise an image component that is comprised of multiple scans of MCUs/data units that are in turn comprised of at least one MCU/data unit segment. Each MCU/data unit segment is successively scanned. The MCU/data unit segment is then reconstructed using multiple entropy decoders operating in parallel on different scans of each MCU/data unit segment.

Abstract: Methods and systems for frequency generation may comprise a circuit with a first input coupled to receive a first satellite signal at a first satellite downlink frequency, a second input coupled to receive a second satellite signal at a second satellite downlink frequency, and a first analog-to-digital converter (ADC) having an input coupled to receive the first satellite signal. The first ADC may be configured to create a first digital output signal representing the first satellite signal. A second ADC having an input coupled to receive the second satellite signal may be configured to create a second digital output representing the second satellite signal. The circuit may comprise a dielectric resonator oscillator having an output and a clock generator circuit having an input coupled to the oscillator output and configured to output one or more clocks used by the first and second ADCs.

Abstract: A method, system and computer program for decompressing video data, storing the compressed video data in such a way that random access is possible and the data can be mapped efficiently into existing memory systems and interface protocols. The compression is accomplished via lossless compression using an algorithm optimized for video data. Due to the compressed format, data transmission consumes less bandwidth than using uncompressed data and prevents degradation in the decoded video.

Abstract: A MSO deploying a standard OLT, and installed with ONUs to be used by customers to whom the MSO can connect using optical fiber. For customers that cannot be reached with optical fiber, the MSO deploys a converter between the optical fiber and the coax network so that the MSO can use the same standard OLT, and use CNUs for those customers attached to the coax network.

Abstract: Methods and systems for a switchable diplexer with physical layout to provide isolation may comprise a diplexer comprising bandpass filters, the bandpass filters having a predetermined passband, and switches coupled to the passband filters and configured to select one of the plurality of bandpass filters, where the bandpass filters are arranged in groups of bandpass filters, a first with an E-band bandpass filter with a passband between 475 MHz and 675 MHz and an F-band bandpass filter having a passband between 650 MHz and 875 MHz, the E-band and F-band bandpass filters being electrically arranged in parallel relation to one another, and a second comprising a D-band bandpass filter with a passband between 1125 MHz and 1675 MHz and a D-low band bandpass filter with a passband between 1125 MHz and 1225 MHz, the D-band and D-low band bandpass filters being electrically arranged in parallel relation to one another.