Abstract: Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Abstract: A data processing system comprising a plurality of interconnected nodes, each node comprising a media processor and one or more ports, each port connected to a respective media processor. Each port is configured to be active or passive, an active port being arranged, upon receipt of data, to transfer the received data to its output, a passive input port being arranged, upon receipt of data, to retain the received data and to transmit the received data to its output when the received data reaches a specific size, and a passive output port being arranged to trigger the receipt of data when the data capacity of the output port reaches a specific size.

Abstract: An integrated circuit voltage regulator uses a simple CMOS structure to implement a High Unity Gain BandWidth voltage regulator providing for low voltage ripple at the output of the regulator up to high frequencies in the hundreds of MHz range. A transconductor first stage is followed by an impedance cancellation second stage allowing DC gain to be set completely independently of the bandwidth.

Abstract: Systems and methods for canceling cross-coupled satellite signals in a LNB IC include receiving a first satellite signal at a first pin of the LNB IC and adjusting the first satellite signal by applying a first adaptive filter to the first satellite signal signal, the first adaptive filter having first filter coefficients; combining the adjusted first satellite signal with a second satellite signal received at a second pin of the LNB IC to generate a first combined satellite signal; measuring the total output power of the combined satellite signal; changing the filter coefficients of the first adaptive filter; remeasuring the total output power of the first combined satellite signal after the changing of the first filter coefficients to determine whether the total power of the first combined satellite signal has decreased.

Abstract: Systems and methods are provided for selecting data from intermediate frequency signals, corresponding to received signals (e.g., satellite signals) carrying modulated data, using digital channelizer switches. An example digital channelizer switch may comprise a plurality of high speed analog-to-digital converters configured to digitize the intermediate frequency signals; a plurality of digital channelizers configured to digitally tune data from the digitized intermediate frequency signals; a multiplexer configured to select one or more digitized intermediate frequency signal generated by the plurality of high speed analog-to-digital converters as inputs to the plurality of digital channelizers; and a high speed digital-to-analog converter configured to generate an analog output signal using digitally tuned data by the digital channelizer, from at least one digitized intermediate frequency signal.

Abstract: Methods and systems for frequency generation may comprise a circuit with a first input coupled to receive a first satellite signal at a first satellite downlink frequency, a second input coupled to receive a second satellite signal at a second satellite downlink frequency, and a first analog-to-digital converter (ADC) having an input coupled to receive the first satellite signal and an output. The first ADC may be configured to create a first digital output signal representing the first satellite signal. A second ADC having an input coupled to receive the second satellite signal and an output may be configured to create a second digital output representing the second satellite signal. The circuit may comprise a dielectric resonator oscillator having an output and a clock generator circuit having an input coupled to the oscillator output and configured to output one or more clocks used by the first and second ADCs.

Abstract: A system for calibrating time interleaved ADCs is disclosed and may include a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, the time interleaved ADC comprising: a plurality of active slices, and a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices. An output of each reference slice may be used to correct distortion in an output of the corresponding active slice. Each active slice may sample an input signal at a first rate and each associated reference slice may sample the input signal at a second rate, the second rate being slower than the first rate. Each sample taken by one of the plurality of reference slices may then be taken concurrent with a sample taken by the associated active slice. Each reference slice may include a reference sampling module and a dummy load.

Abstract: Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by a processor; a cache manager to manage, a cache within the memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and a search module to receive from the cache manager an identifier of a requested data item, search the plurality of pointer entries for the identifier of the requested data item and, if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, provide the cache manager with the pointer from the detected entry. Other embodiments are described and claimed.

Abstract: Systems and methods for correcting frequency error in a received signal include: receiving a satellite signal, the satellite signal having a bandwidth and a center frequency; determining the profile of the satellite signal; computing the center frequency of the satellite signal based on the profile of the received signal; and generating a reference signal at the computed center frequency. The systems and methods may further include computing a center frequency of each of a plurality of satellite signals based on the computed center frequency. Determining the profile may include sweeping a tuner above and below a given reference frequency; measuring the received signal strength during the sweeping operation; and determining the profile based on the received signal strength.

Abstract: A low noise block circuit includes a first input signal trace configured to receive a first satellite signal centered at a first frequency; a second signal trace configured to receive a second satellite signal centered at a second frequency; a combiner having a first input connected to the first input signal trace and a second input connected to the second signal trace, and configured to combine the first and second satellite signals to generate and output a combined satellite signal; and an analog-to-digital converter element having a first input coupled to receive the combined satellite signal, and configured to convert the combined satellite signal from an analog signal to a digital signal.

Abstract: Methods and systems for integrated circuit design using dynamic voltage scaling may comprise (a) designing an IC to meet a voltage dependent frequency specification, the IC design including feedback circuitry for controlling a power supply voltage to a fabricated instance of the IC design, (b) characterizing a fabrication process for corner lots for the IC design at a range of power supply voltage levels achievable by the feedback circuitry; (c) validating the IC design against the fabrication process if the frequency specification is achievable for essentially all instances of the IC design fabricated, wherein the feedback circuitry in each IC resulting from the IC design is operable to respectively adjust the power supply voltage of each IC resulting from the IC design by reducing the power supply voltage if the IC is from a fast corner lot and increasing power supply voltage if from a slow corner lot.

Abstract: Systems and methods for dynamically adjusting transmit gain in a transceiver. The gain is adjusted in order to provide the maximum gain. The amount of distortion is measured. The gain is increased until the distortion reaches a predetermined limit. The gain of several components can be adjusted independently.

Abstract: A communication device includes a communication port including network interface circuitry; and a power control module configured to awaken the communication device from a sleep mode, determine whether a network is present at the communication port, and to return the communication device to the sleep mode if it is determined that a network is not present at the communication port.

Abstract: Systems and methods for selecting, combining and duplexing signals in a communications network. Several configurations of diplexers and channel selectors are disclosed which use filters, combiners and splitters to select and combine which the signals to be either received or transmitted.

Abstract: A system includes a first circuit and a second circuit. The first circuit includes a first MOS transistor having a gate and a drain. The first circuit is configured to receive a radio frequency (RF) signal at the gate of the first MOS transistor. The drain of the first MOS transistor is configured to output a first current that is proportional to the square of the input voltage of the RF signal while receiving the RF signal. The second circuit includes a second MOS transistor having a source configured to receive a first current from the first circuit. The second MOS transistor is biased in a triode region and has a channel resistance between the source and a drain. The second circuit is configured to output a voltage proportional to the value of the power of the RF signal received by the first circuit.

Abstract: Systems and methods for scheduling network communications in a managed network can include a Network Controller discovering a plurality of network nodes; the Network Controller classifying the discovered network nodes into two or more classifications of node for node-level prioritization of network communications; the Network Controller receiving reservation requests from at least some of the plurality of network nodes, wherein the reservation requests request one or more time slots for their respective network nodes in an upcoming communication window; and the Network Controller assigning time slots in the upcoming communication window to one or more network nodes in response to reservation requests, wherein the assignment is based on a priority of the network nodes and wherein the priority is assigned to the nodes according to their classification.

Abstract: A method and an apparatus from such method for designing an integrated circuit (IC) that mitigates the effects of process, voltage, and temperature dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits. Conventional design process takes into account power supply voltage Vdd as a variable that must be considered in a skewed corner analysis. The disclosure teaches that the IC design process can be substantially simplified by essentially factoring out voltage based variations in corner lot analysis for IC designs that include dynamic voltage scaling circuitry, because each fabricated IC die of an IC design having dynamic voltage scaling can individually adjust the applied supply voltage Vdd within a range to offset local process-induced variations in the performance of that specific IC die.

Abstract: A dielectric resonator oscillator includes a dielectric resonator; a transmission line disposed adjacent the dielectric resonator; an active device having an input electrically connected to the transmission line; a matching network having an input electrically connected to an output of the active device and an output configured to be connected to a load; wherein both the transmission line and the active device are positioned sufficiently close to the dielectric resonator to form part of a resonant circuit with the dielectric resonator.

Abstract: Circuits, systems, and methods for assembling a composite signal include a frequency translation circuit coupled to receive an input signal and operable to generate a plurality of frequency-translated versions of the input signal at a respective plurality of different frequencies, the plurality of frequency-translated input signals defining a group of frequency translated signals. The plurality of frequency translated signals may each be processed to provide a composite signal.

Abstract: Various systems and methods for probing a communication channel. These systems and methods transmit an error vector probe packet from a first transmitter while a second transmitter is active and transmitting. A network device may receive the error vector probe packet and measure an error vector magnitude based on the received error vector probe packet. Using the error vector magnitude, the network device estimates channel characteristics such as signal-to-noise ratio, data capacity, etc. The transmission can occur when more than one transmitter is active and transmitting. At least some of the other transmitters are active and transmit an analog zero signal, e.g., all digital zeros on the input to the digital-to-analog converter of a network device when an error vector probe packet is transmitted.