Abstract: A programmable display controller for use in a digital imaging system has a video control register, a data access controller and a programmable modulator. The programmable display control is designed to be used with a digital imaging systems, such as digital cameras, having a variety of display different devices that require respective different control signals, different image signal modulations, and so on. The video control register stores video mode bits indicating the type of video signal to output. The data access controller has a buffer for requesting image data and storing the requested image data in the buffer. The programmable modulator, in response to the video mode bits, generates a video signal from the image data stored in the buffer. In some embodiments, a decoder detects and decodes a link code in received image data. An address generator is responsive to the decoder and outputs a link address corresponding to the decoded link code for fetching image data that is stored at the link address.

Abstract: A shared output visible imager pixel array combines a high optical fill factor with low read noise. A relatively small group of pixels are connected to a relatively short common bus line. An amplifier located in close proximity with the pixels is connected to the common bus line and shared among the pixels. By reducing the amount of amplifier circuitry associated with each pixel, the optical fill factor is increased. Also, since the bus line is relatively short, the bus capacitance is much lower relative to the traditional passive-pixel designs. On average, the transistor count per pixel can be less than two, for large arrays.

Abstract: A radiation receiving apparatus that comprises a pixel array and one or more microlenses located between the source of radiation and a less sensitive pixel in the pixel array. The arrangement of microlenses in a radiation receiving apparatus utilize a system architecture that recognizes that within a pixel array, there is typically a less sensitive pixel (i.e. one receiving light in the blue spectrum) and a more sensitive pixel (i.e. one receiving light in the red spectrum). A microlens is placed in physical proximity to the less sensitive pixel in order to decrease the inherent difference in sensitivity between the less sensitive pixel and the more sensitive pixel, in turn increasing the intensity of radiation incident upon the detecting area of the less sensitive pixel. The detecting area may include a photogate or a photodiode for sensing radiation.

Abstract: A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.

Abstract: A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.

Abstract: An imaging array of active pixel sensors uses a compact three transistor CMOS implementation for each pixel. A current source at the top of each column creates a distributed feedback amplifier for each pixel in a selected row. The reset amplifier acts as a variable resistance in the source-follower amplifier feedback circuit. The variable resistance is controlled by a range reset voltage applied to the reset amplifier thereby nulling the photodiode reset noise.

Abstract: The invention dynamically compensates for differences in data rates. In one embodiment, the status of an input buffer is monitored and used to change the number of oversamples within a frame. In another embodiment, a high frequency clock in the system is used to stall the codec for one clock. In both ways, distortion due to differences in data rates is reduced.

Abstract: An analog-to-digital converter in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom. By weighting and mixing outputs of adjacent comparators in proportions calculated to provide an interpolated output of a virtual comparator between the actual comparators, many such virtual comparators can be created without the need for additional fixed hardware elements in the converter. By doing so, the converter is able to produce a digital output having n bits using only N actual hardware elements for comparing signals, where N<2n−1. Each of the plurality of comparators in the converter has an input for an enabling signal, which enabling signal can be manipulated to enable or disable individual comparators and to modify their outputs. A method for converting an analog input signal into a digital signal using such a converter.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.

Abstract: The present invention provides a method and system for switching between browser and video modes in a standalone VCD-ROM system including a VCD player and a VCD-ROM disk. A browser program is first executed in the VCD-ROM system. The browser program allows a user to navigate through the content of the VCD-ROM disk by selecting hypertext links. The hypertext links are selected by clicking on clickable text, buttons, and graphics. The system also allows the user to play a video by selecting an associated hypertext link. When the video is selected, the method of the present invention saves the return address and the address of the video. The video is then played on the video system. When the video is finished playing, the method of the present invention reloads the return address into the system. This returns the system to the original browser mode of the browser.

Abstract: A spectral shaping PCM modem communication system uses a symbol encoder to encode a data bit stream into a PCM symbol stream. A plurality of different frames are formed from the PCM symbol stream. Performance metrics are computed for each possible frame and its inversion so a decision can be made in order to select a most desirable frame and inversion Delays are injected in the data flow to allow a look-ahead and thus provide for better frame selection and inversion decisions. A channel multiplexer combines decision bits and output frames to form encoded output frames that are fed to a digital channel connected to a telephone network wherein they are converted to analog signal. A corresponding decoder converts analog signals from the telephone network to digital signals. A timing recovery and equalization means corrects sample timing and removes inter-symbol interference effects introduced by telephone networks.

Abstract: The present invention provides a library of cells that can be stored in a computer readable memory and used in the computer-aided design of integrated circuits. Some of the cells in this cell library describe circuits having variable delays. In this cell library, two different cells are able to represent circuits that can be configured to delay signal transmission by different time periods while still being contained within substantially equal areas on a silicon substrate. One way that the cell library allows for such a configuration is if the two cells both represent a delay circuits that contains an n-channel transistor coupled to a p-channel transistor. Each n-channel and p-channel transistor has an n- or p-channel gate respectively, and this gate can be described as having a length and a width. When the length of the n-channel gate in the first delay circuit differs from the length of the n-channel gate in the second delay circuit, the delay time associated with each circuit will also differ.

Abstract: A spectral shaping PCM modem communication system uses a symbol encoder to encode a data bit stream into a PCM symbol stream. A plurality of different frames are formed from the PCM symbol stream. Performance metrics are computed for each possible frame and its inversion so a decision can be made in order to select a most desirable frame and inversion. Delays are injected in the data flow to allow a look-ahead and thus provide for better frame selection and inversion decisions. A channel multiplexer combines decision bits and output frames to form encoded output frames that are fed to a digital channel connected to a telephone network wherein they are converted to analog signal. A corresponding decoder converts analog signals from the telephone network to digital signals. A timing recovery and equalization means corrects sample timing and removes inter-symbol interference effects introduced by telephone networks.

Abstract: A device for use in a modem configuration that enables the transfer of data from a host signal processor (HSP) to an A/D-D/A converter or CODEC with less data loss, with low noise and that can send data at varying carrier frequencies without changing the size of the buffers. The device further allows for data transfer that is flexible with any given modulation scheme, carrier frequency or baud frequency to conform with the V.34, V90, as well as prior and subsequent recommendations. The device further includes a counter for counting the number of data samples transferred between the CODEC and the HSP and for alerting the HSP to avoid an overflow condition. The counter is further configured to count beyond the physical size of the buffer in order to simplify operation in an overflow condition. A transmit buffer is included for transferring data from the HSP to the CODEC.

Abstract: A method and apparatus for performing voltage-mode sample and hold functions while avoiding nonlinear charge injection. The method comprises oversampling an input signal and sampling an error signal, not the input signal directly, and through signal processing causing the error signal to be reduced to low amplitude. First order and higher order voltage-mode sample and hold circuitry embodiments are provided.

Abstract: An apparatus and method is provided for reducing the area of integrated circuits using cells with multiple unrelated gates. A netlist is generated which includes cells and interconnecting nets. Each cell represents a circuit and each net represents an interconnection between cells. Combinable cells of the netlist are paired to create a list. A combinable cell represents a circuit having at least one transistor formed on a substrate area. This transistor includes a diffusion layer directly coupled to a voltage source via a diffusion contact, wherein the diffusion contact is positioned adjacent an outer edge of the substrate area. A combinability score is calculated for each pair of combinable cells of the list. Each combinability score is calculated as a function of the number of nets representing direct or indirect interconnections between a pair of combinable cells. The pair of combinable cells corresponding to the highest combinability score is removed from the netlist. Thereafter, a combined cell is added.

Abstract: Techniques for applying a periodic signal to an interpolated digital signal at the input of a delta-sigma modulator to reduce noise tones a DC noise level in the output of a delta-sigma DAC. The duty cycle of the periodic signal can be adjusted to substantially cancel the DC noise level. In one embodiment, the DC noise level is first determined by, e.g., a calibration process. Then, the duty cycle of the periodic signal is adjusted according to the determined DC noise level.

Abstract: The invention dynamically compensates for differences in data rates for multistreamed systems. Any or all of the streams in a multistreamed system may be individually compensated at one time. In one embodiment, the status of an input buffer is monitored and used to change the number of oversamples within a frame of one of the number of streams. In another embodiment, a high frequency clock in the system is used to stall one of the streams for one or more clock cycles. In both ways, distortion due to differences in data rates is reduced.

Abstract: A semiconductor device with an embedded PCI 2.1 compliant bridge provides expanded functionality as system-level implementations of a PCI-to-PCI bridge, and enhances the level of integration possible. The embedded PCI-to-PCI bridge allows the creation of multi-function, multimedia add-on cards supporting multiple devices. Multi-function, multimedia subsystems that provide audio, graphics, MPEG, etc., are mapped into a bridged-to PCI-bus that keeps such traffic off the main PCI-bus. The advantage for the system or add-in card vendor is that the various multimedia chips that are combined can come from different sources, providing an optimized and highly customized combination of functions.