Patents Assigned to EverSpin Technologies, Inc.
  • Publication number: 20200373481
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Sarin A. DESHPANDE, Kerry Joseph NAGEL
  • Patent number: 10847711
    Abstract: A method of fabricating a magnetoresistive device includes etching a magnetoresistive stack using a first etching process to form one or more sidewalls, and etching the stack using a second etching process after forming the one or more sidewalls. Wherein, the second etching process may be relatively more isotropic than the first etching process.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: November 24, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Jon Slaughter, Cong Hai, Hyunwoo Yang, Naganivetha Thiyagarajah, Shukai Ye
  • Patent number: 10847715
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 24, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 10825500
    Abstract: A magnetoresistive memory device that stores data in the synthetic antiferromagnet (SAF) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, where an unbalanced SAF that includes ferromagnetic layers having different magnetic moments is used to lower the switching barrier for the SAF and allow for writing data values to the SAF using lower currents and magnetic fields than would be required for a balanced SAF.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 3, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Han-Jong Chia, Sumio Ikegawa, Michael Tran, Jon Slaughter
  • Publication number: 20200343300
    Abstract: A magnetoresistive device may include a first ferromagnetic region, a second ferromagnetic region, and an intermediate region positioned between the first ferromagnetic region and the second ferromagnetic region. The intermediate region may be formed of a dielectric material and comprise at least two different metal oxides.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Jijun SUN
  • Patent number: 10811597
    Abstract: A magnetoresistive device with a magnetically fixed region having at least two ferromagnetic regions coupled together by an antiferromagnetic coupling region. At least one of the two ferromagnetic regions includes multiple alternating metal layers and magnetic layers and one or more interfacial layers. Wherein, each metal layer includes at least one of platinum, palladium, nickel, or gold, and the interfacial layers include at least one of an oxide, iron, or an alloy including cobalt and iron.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Everspin Technologies, Inc.
    Inventor: Jijun Sun
  • Patent number: 10809320
    Abstract: Various means for improvement in signal-to-noise ratio (SNR) for a magnetic field sensor are disclosed for low power and high resolution magnetic sensing. The improvements may be done by reducing parasitic effects, increasing sense element packing density, interleaving a Z-axis layout to reduce a subtractive effect, and optimizing an alignment between a Z-axis sense element and a flux guide, etc.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 20, 2020
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Phillip G. Mather, Anuraag Mohan
  • Publication number: 20200328252
    Abstract: A method of manufacturing a magnetoresistive device may include forming a first ferromagnetic region, forming an intermediate region on or above the first ferromagnetic region. The intermediate region may be formed of a dielectric material and include nitrogen. The method may also include forming a second ferromagnetic region on or above the intermediate region.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 15, 2020
    Applicant: Everspin Technologies, Inc.
    Inventor: Jijun SUN
  • Patent number: 10794968
    Abstract: A magnetic field sensor that includes a differential bridge in which each path of the bridge includes a first type of magnetic field sensing device and a second type of magnetic field sensing device. The first and second types of magnetic field sensing devices differ in the magnetic moment imbalance present in the synthetic antiferromagnets (SAFs) included in their reference layers such that that different types of devices produce a different response to perpendicular magnetic fields, but the same response to in-plane magnetic fields. Such different magnetic moment imbalances in the SAFs of magnetic field sensing devices included in a bridge allow for accurate sensing of perpendicular magnetic fields in a differential manner that also cancels out interference from in-plane fields. Techniques for producing such magnetic field sensing devices on an integrated circuit are also presented.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: October 6, 2020
    Assignee: Everspin Technologies, Inc.
    Inventor: Jon Slaughter
  • Publication number: 20200295255
    Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (1) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may he disposed on the first layer.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 17, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Srinivas V. PIETAMBARAM, Bengt J. AKERMAN, Renu WHIG, Jason A. JANESKY, Nicholas D. RIZZO, Jon M. SLAUGHTER
  • Patent number: 10777738
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 15, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Sarin A. Deshpande, Kerry Joseph Nagel
  • Publication number: 20200287128
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Sarin A. DESHPANDE
  • Publication number: 20200286950
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Thomas ANDRE, Sarin A. DESHPANDE
  • Publication number: 20200266235
    Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).
    Type: Application
    Filed: May 8, 2020
    Publication date: August 20, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Jijun SUN, Sanjeev AGGARWAL, Han-Jong CHIA, Jon M. SLAUGHTER, Renu WHIG
  • Publication number: 20200243761
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer. (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sarin A. DESHPANDE, Kerry Joseph NAGEL, Chaitanya MUDIVARTHI, Sanjeev AGGARWAL
  • Publication number: 20200235288
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 23, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sumio IKEGAWA, Han Kyu LEE, Sanjeev AGGARWAL, Jijun SUN, Syed M. ALAM, Thomas ANDRE
  • Publication number: 20200235289
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 23, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Thomas ANDRE, Frederick MANCOFF, Sumio IKEGAWA
  • Patent number: 10707410
    Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 7, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Patent number: 10700123
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande
  • Patent number: 10700268
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 30, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Sarin A. Deshpande