Patents Assigned to EverSpin Technologies, Inc.
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Publication number: 20250113741Abstract: A magnetoresistive random-access memory (MRAM) device includes a magnetoresistive tunnel junction (MTJ) device, an electrode, and a coupling layer. The MTJ device includes a free layer, a fixed layer, and a tunnel barrier layer positioned between the free layer and the fixed layer. The coupling layer is positioned between and coupling the electrode and the MTJ device. The coupling layer includes spin Hall channel (SHC) material. The free layer, the fixed layer, and the tunnel barrier layer are stacked in a first direction to form MTJ device. The electrode is nonaligned with the MTJ device such that the electrode is spaced away from the MTJ in a second direction that is different from the first direction.Type: ApplicationFiled: September 26, 2024Publication date: April 3, 2025Applicant: Everspin Technologies, Inc.Inventors: Sumio IKEGAWA, Kerry Joseph NAGEL, Raj KUMAR, Syed M. ALAM
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Publication number: 20250068341Abstract: Systems and techniques include identifying a network layer for performing a memory operation, identifying a subset of a plurality of configuration bit clusters of a non-volatile distributed memory that are mapped to the identified network layer using a cluster mapping, in response to identifying the subset of the plurality of configuration bit clusters, activating the subset of the plurality of configuration bit clusters, loading network component data from the subset of the plurality of configuration bit clusters into a local buffer, and applying the network component data to the network layer for performing the memory operation.Type: ApplicationFiled: February 28, 2024Publication date: February 27, 2025Applicant: Everspin Technologies, Inc.Inventors: Syed M. ALAM, Michael SADD, Jacob T. WILLIAMS
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Publication number: 20250061933Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.Type: ApplicationFiled: November 1, 2024Publication date: February 20, 2025Applicant: Everspin Technologies, Inc.Inventors: Syed M. ALAM, Yaojun ZHANG, Frederick NEUMEYER
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Publication number: 20250063953Abstract: A magnetoresistive device includes a magnetically fixed region and a magnetically free region positioned on opposite sides of a tunnel barrier region. One or more transition regions, including at least a first transition region and second transition region, is positioned between the magnetically fixed region and the tunnel barrier region. The first transition region includes a non-ferromagnetic transition metal and the second transition region includes an alloy including iron and boron.Type: ApplicationFiled: October 31, 2024Publication date: February 20, 2025Applicant: Everspin Technologies, Inc.Inventors: Renu WHIG, Sumio IKEGAWA, Jon SLAUGHTER, Michael TRAN, Jacob Wang CHENCHEN, Ganesh Kolliyil RAJAN
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Publication number: 20250031580Abstract: A method of manufacturing a magnetoresistive device may comprise providing a magnetoresistive structure comprising a bottom electrode, a magnetoresistive stack, and a top electrode. The method may include removing at least a portion of the top electrode using a first etch, where the first etch is performed in the presence of a first gas mixture. Methods of manufacturing the magnetoresistive device may include removing at least a portion of the magnetoresistive stack and the bottom electrode using a second etch, wherein the second etch is performed in the presence of a second gas mixture. The first and second gas mixture may comprise a hydrocarbon including a carbon-carbon double bond or a carbon-carbon triple bond.Type: ApplicationFiled: July 18, 2024Publication date: January 23, 2025Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, SHIMON, Sanjeev AGGARWAL
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Publication number: 20250029645Abstract: The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.Type: ApplicationFiled: October 8, 2024Publication date: January 23, 2025Applicant: Everspin Technologies, Inc.Inventor: Syed M. ALAM
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Patent number: 12181539Abstract: Various means for improvement in signal-to-noise ratio (SNR) for a magnetic field sensor are disclosed for low power and high resolution magnetic sensing. The improvements may be done by reducing parasitic effects, increasing sense element packing density, interleaving a Z-axis layout to reduce a subtractive effect, and optimizing an alignment between a Z-axis sense element and a flux guide, etc.Type: GrantFiled: March 29, 2024Date of Patent: December 31, 2024Assignee: Everspin Technologies, Inc.Inventors: Phillip G. Mather, Anuraag Mohan
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Publication number: 20240419361Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.Type: ApplicationFiled: August 22, 2024Publication date: December 19, 2024Applicant: Everspin Technologies, Inc.Inventors: Syed M. ALAM, Iftekhar RAHMAN, Pedro SANCHEZ
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Publication number: 20240420796Abstract: A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.Type: ApplicationFiled: June 11, 2024Publication date: December 19, 2024Applicant: Everspin Technologies, Inc.Inventors: Syed M. ALAM, Jacob T. WILLIAMS, Michael A. SADD, Kerry Joseph NAGEL, Sumio IKEGAWA, Frederick B. MANCOFF, Sanjeev AGGARWAL
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Patent number: 12165684Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.Type: GrantFiled: April 10, 2023Date of Patent: December 10, 2024Assignee: Everspin Technologies, Inc.Inventors: Syed M. Alam, Yaojun Zhang, Frederick Neumeyer
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Patent number: 12167702Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.Type: GrantFiled: March 20, 2023Date of Patent: December 10, 2024Assignee: Everspin Technologies, Inc.Inventors: Sumio Ikegawa, Han Kyu Lee, Sanjeev Aggarwal, Jijun Sun, Syed M. Alam, Thomas Andre
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Publication number: 20240397731Abstract: A magnetoresistive stack, including an electrically conductive material, and a seed region disposed above the electrically conductive material and including chromium (Cr). A chromium content of the seed region is large enough to render the seed region substantially non-magnetic. The magnetoresistive stack includes a fixed magnetic region disposed above the seed region. The fixed magnetic region includes a synthetic antiferromagnetic structure including a first ferromagnetic region disposed above the seed region, a coupling layer disposed on and in contact with the first ferromagnetic region, and a second ferromagnetic region disposed on and in contact with the coupling layer. The magnetoresistive stack includes one or more dielectric layers disposed above the second ferromagnetic region, and a free magnetic region disposed above the one or more dielectric layers.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Applicant: Everspin Technologies, Inc.Inventors: Jijun SUN, Sanjeev AGGARWAL, Han-Jong CHIA, Jon SLAUGHTER, Renu WHIG
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Patent number: 12142309Abstract: The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.Type: GrantFiled: June 23, 2022Date of Patent: November 12, 2024Assignee: Everspin Technologies, Inc.Inventor: Syed M. Alam
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Patent number: 12137616Abstract: A method of fabricating a magnetoresistive device includes forming a magnetically fixed region on one side of an intermediate region. Forming the magnetically fixed region may include forming a first ferromagnetic region and forming an antiferromagnetic coupling region on one side of the first ferromagnetic region. The method may also include treating a surface of the coupling region by exposing the surface to a gas, and forming a second ferromagnetic region on the treated surface of the coupling region.Type: GrantFiled: November 14, 2018Date of Patent: November 5, 2024Assignee: Everspin Technologies, Inc.Inventor: Jijun Sun
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Publication number: 20240361906Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.Type: ApplicationFiled: July 5, 2024Publication date: October 31, 2024Applicant: Everspin Technologies, Inc.Inventors: Syed M. ALAM, Cristian P. MASGRAS
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Publication number: 20240341199Abstract: A method of fabricating a magnetoresistive device may comprise forming an electrically conductive region and forming a first seed region on one side of the electrically conductive region. A surface of the first seed region may be treated by exposing the surface to a gas. A second seed region may be formed on the treated surface of the first seed region. The method may also comprise forming a magnetically fixed region on one side of the second seed region.Type: ApplicationFiled: June 17, 2024Publication date: October 10, 2024Applicant: Everspin Technologies, Inc.Inventor: Jijun SUN
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Patent number: 12112067Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.Type: GrantFiled: August 9, 2022Date of Patent: October 8, 2024Assignee: Everspin Technologies, Inc.Inventors: Syed M. Alam, Iftekhar Rahman, Pedro Sanchez
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Publication number: 20240315145Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.Type: ApplicationFiled: May 24, 2024Publication date: September 19, 2024Applicant: Everspin Technologies, Inc.Inventor: Sumio IKEGAWA
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Publication number: 20240306516Abstract: Aspects of the present disclosure are directed to magnetoresistive stacks including regions having increased height-to-diameter ratios. Exemplary magnetoresistive stacks (for example, used in a magnetic tunnel junction (MTJ) magnetoresistive device) of the present disclosure include one or more multilayer synthetic antiferromagnetic structures (SAFs) or synthetic ferromagnetic structures (SyFs) in order to promote stability of the SAF or SyF, e.g., for smaller-sized MTJs.Type: ApplicationFiled: May 15, 2024Publication date: September 12, 2024Applicant: Everspin Technologies, Inc.Inventor: Jijun SUN
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Patent number: RE50331Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.Type: GrantFiled: April 8, 2022Date of Patent: March 4, 2025Assignee: Everspin Technologies, Inc.Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff