Abstract: A high voltage analog solid state switch is disclosed which includes a pair of MOS FET's 10 and 20 having commonly coupled sources 11 and 21 and commonly coupled gates 13 and 23. A photovoltaic generator 30 and an opto-coupler 40 are connected in parallel between the commonly coupled gates and sources. The input node is connected to the drain of one transistor 10 while an output node is connected to the drain of the other transistor 20. The switch is turned on by application of light 32 to generator 30 to thereby positively bias the gates 13 and 23 and cause transistors 10 and 20 to conduct. The switch is turned off by application of light 42 to coupler 40 to thereby short the commonly coupled sources 11 and 21 to the commonly coupled gates 13 and 23.

Abstract: A process for fabricating self-aligned regions of metal silicide on bipolar integrated circuits having self-aligned polycrystalline silicon emitters and base contacts includes the steps of depositing a layer of polycrystalline silicon across the surface of the structure, patterning the polycrystalline silicon to define the emitters and base contacts as well as resistors and diodes, heating the structure to transfer desired conductivity dopants from the polycrystalline silicon into the underlying structure, forming a protective layer over those regions of the structure where metal silicide is not desired, depositing a layer of refractory metal across the entire structure, and reacting the refractory metal with the underlying silicon to form metal silicide.

Abstract: A lead wire bonding machine is described for ball bonding the end of a lead wire held in a bonding tool to a die pad of an integrated circuit chip and for wedge bonding a segment of the lead wire spaced from the ball bond to a lead frame finger during successive ball bond wedge bond cycles. The bonding machine includes a variable linear drive such as a solenoid or small linear motor coupled to the bonding head for applying the first bond force to the bonding tool during ball bonding and the second bond force to the bonding tool during wedge bonding. A control circuit coupled to the solenoid or other variable linear drive delivers a first current having a desired profile or amplitude wave envelope for applying the first bond force with a first force profile during ball bonding to die pads and by delivering a second current having a desired profile or amplitude wave form for applying the second bond force with a second force profile during wedge bonding to lead frame fingers.

Abstract: An improved lead wire ball bonding machine for bonding wire leads between an integrated circuit chip and the lead frame on which the chip is mounted is provided with a bonding tool position sensor coupled to receive the Z-motion velocity waveform signal to the servo motor which drives the bonding head and bonding tool. This sensor detects the signal level and direction of change or polarity of the Z-motion velocity waveform signal for determining the location of the bonding head and bonding tool. The bonding tool position sensor is coupled and adjusted for generating a first output signal corresponding to a first location of the bonding head and bonding tool during motion downward to the die pad of an integrated circuit chip prior to contact by the bonding tool and lead wire for ball bonding.

Abstract: An automatic test system for parallel loading of data into pin registers 100 associated with pins of a device being tested includes data bus 130 for transmitting data; an address bus 120 for transmitting addresses; a set of pin registers 100, each having a unique address and each coupled to receive information from the data bus 130; a participate register 150 coupled to data bus 130 and to each of registers 100 for enabling selected ones of registers 100 to receive data from the data bus at the same time; an address decoder 110, 180 connected to the address bus 120, to each of registers 100, and to the participate register 150, for enabling one of the pin registers 100 or the participate register 150 to receive data from the data bus, the data for the participate register 150 comprising the addresses of each of the selected ones of pin registers 100 which are to receive data from the data bus in parallel.

Abstract: A self-aligned element antiblooming structure for application to charge-coupled devices includes a region in the substrate in which the charge-coupled device is fabricated into which both a P and N conductivity type impurity are introduced. By introducing impurities of different diffusivities, a sink region is created between two very narrow antiblooming barriers. Using appropriate process controls, the potential height of the antiblooming barriers may be adjusted to drain excess charge accumulating in the substrate adjacent the antiblooming barriers. In this manner the antiblooming function is accomplished using only a minimal area of the substrate. The invention is applicable to charge-coupled devices utilizing a variety of different clocking schemes, and to charge-coupled device image sensors using buried channels.

Abstract: A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by the analog-to-digital converter under test. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the analog-to-digital converter under test.

Abstract: An improved TTL tristate device with reduced output capacitance incorporates an active discharge sequence of three elements including first and second active transistor elements (Q8, Q7) in an inversion coupling and a third passive element comprising a passive diode cluster (D3, D4, D5) coupled between the base of the second transistor element (Q7) and the enable gate. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor (Q7) when the enable gate (A) is at high potential for operation of the output device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor (Q7) when the enable gate (A) is at low potential for operation of the output device in the high impedance third state with reduced output capacitance.

Abstract: A circuit and method for enabling/disabling a differential signal output from a memory device, such as a bipolar static random access memory, is disclosed. A split bias, current steering circuit includes a first differential amplifier for steering a current I.sub.D along a first current path when a first selected differential input signal, corresponding to a first logic state, is coupled to a first input terminal of said first differential amplifier; and includes a second differentialamplifier for steering current I.sub.D along a second current path when a second selected differential input signal, corresponding to a second logic state, is coupled to a second input terminal of said second differential amplifier. An output stage produces a selected logic output signal according to which of said first and second current paths is selected to steer current I.sub.D. A split bias enable/inhibit stage provides controlled operation of the first and second differential amplifiers.

Abstract: A microprocessor data processing system (1700) includes system units (50, 1704) connected to a bus (1702), with a bus arbiter (1712) and a protocol for assigning bus access to the system units (50, 1704). The microprocessor (50) executes both arithmetic operations and floating point operations. A microcontrol store (162) stores common instructions usable in different floating point operations. A PLA (180) supplies addresses to microcontrol store (162) and provides a signal indicating floating point instruction type. The microprocessor (50) includes a pending interrupt register (250) connected to mask and enable logic (268). The mask and enable logic (268) is connected to a priority encoder (278), which is connected to an interrupt latch (282). The latch (282) supplies outputs to generate a current state storage address.

Abstract: A tri-state driver circuit 10 for selectively driving a node of a device under test by applying and switching between two reference voltages, and for selectively operating at a high impedance output state. Two current sources 16 and 18 provide a bridge current that flows through a diode bridge 20 to establish, at nodes A and B, voltages that equal two reference voltages, DRH and DRL. The diode bridge includes resistors R11 and R16 across which the bridge current is switched to accommodate small voltage swings, and also includes clamp diodes CR3-6 to accommodate large voltage swings. A current switch 22 controls the direction of the bridge current and the selection of which of the two reference voltages appears at node A. A current sink 36, 38, and 40 monitors the average voltage of the diode bridge and adjusts it to equal the average of the two reference voltages.

Abstract: A method of defining narrow regions in an underlying integrated circuit structure includes the steps of depositing a first layer of material 30 having selected etching characteristics on the underlying integrated circuit structure, depositing a second layer of material 32 having etching characteristics different from the first layer 30 on the first layer 30, anisotropically etching the first layer 30 and the second layer 32 from all of the underlying integrated circuit structure 26 except for a desired region having a periphery which includes the narrow region, forming a coating 35 of smoothing material over all of the underlying integrated circuit structure 26 except for the first layer 30, and isotropically etching the first layer 30 to remove it from the surface of the underlying integrated circuit structure 26 to thereby define the narrow region 36. Use of the process to fabricate a compact bipolar transistor structure is also disclosed.

Abstract: An improved method for forming a titanium silicide layer comprising placing a silicon layer overcoated with titanium in an ambient atmosphere of ultrapure nitrogen and heating the overcoated layer with radiation from a tungsten-halogen source.

Abstract: A disabling circuit 71 responsive to a control signal 81 generated by applying to an IC pin 86 a signal outside the range of normal operating voltages of the device 16. The disabling circuit 71 grounds the output of are dundant address decoder such as 31 to disable a spare element 37 of the device 16, allowing identification of repaired elements.

Abstract: The suppression of the reverse injection of the carriers in a bipolar transistor, without adversely effecting forward injection, is carried out by modifying the energy gap characteristics of the transistor so that a greater barrier to reverse injection is presented than that which is confronted by the forward injected carriers. The energy gap of the emitter is increased, relative to that of the base, through ion implantation. The ions which are implanted are such that the resulting compound material has a higher energy gap than that of silicon into which they are implanted to selectively modify the emitter region so as to locally increase its energy gap. Preferred materials include carbon and nitrogen.

Abstract: A high speed error correcting random access memory system includes a circuit for generation of a plurality of parity bits from a predetermined combination of data bits of a data word being stored in a random access memory such that these parity bits are stored in memory along with said data bits, and for outputting the data word from said memory system, including correcting for any single bit error in the data word, by a circuit that generates a check word from the data word bits and parity word bits stored in the memory, whose state indicates if any of the data bits are in error, and, if so, proceeds to correct any such erroneous bit. The system also includes a circuit for inserting an erroneous bit of data in memory after the parity bits have been generated, to check operation of the check word generating and output data word correction circuit. The operation of the check word generating circuit can also be suspended so as to enable uncorrected data words to be output by the memory system.

Abstract: A method and circuits are described for sensing and detecting bond attempts and weld attempts during bonding and welding of lead wire. The method and circuitry are particularly applicable for detecting missed ball bonds and missed wedge bonds during bonding of lead wire between the die pad of a microcircuit chip and the lead frame on which the chip is mounted. A sensor (30) or sensing circuit (42) senses the different characteristic electrical condition of the lead wire (11) following a ball bond attempt and following a wedge bond attempt. A bond attempt indicator (45) indicates high resistance in the lead wire following a missed ball bond while weld attempt indicator (46) indicates low resistance in the lead wire (11) following a missed wedge bond. The lead wire (11) is isolated from uncontrolled contacts with ground potential while the lead wire is held in the bonding tool and bonding machine.

Abstract: A static RAM cell (11) is constructed utilizing low resistivity positive and negative power supply leads (13,14), thus eliminating the problem of instability of the data stored within the cell. The negative power supply lead is formed of a first layer of low resistivity polycrystalline silicon/tantalum silicide, and the positive power supply lead is formed of a second layer of polycrystalline silicon. The use of a low resistivity negative power supply lead causes the voltage drop on the negative power supply lead to be substantially reduced as compared with prior art devices, thereby providing during the read operation substantially equal voltages to the gates of the two bistable transistors of each cell, thus eliminating the problem of instability during reading.Depletion load devices (11,12) are formed utilizing the layer of polycrystalline silicon as the source, drain and channel and the layer of polycrystalline silicon/tantalum silicide as the gate.

Abstract: An electrical pulse edge timing adjustment circuit 10 comprising one or more deskew elements 5. In each deskew element, a pulse train is passed through an inverter 20. The falling rate of pulse edges on the inverter output line 21 is controlled by a capacitor 24 and an adjustable current sink 25 which determine the output line capacitance discharge rate. From the output line, pulses are passed to another deskew element which re-inverts the pulses and delays the formerly rising pulse edges. Each current sink is independently adjustable to allow different delays in the rising and falling edges.

Abstract: A lateral transistor structure having a self-aligned base and base contact is provided, together with a method for fabricating such a structure in which the base width is controlled by lateral diffusion of an impurity through a polycrystalline silicon layer. The resulting zone of impurity changes the etching characteristics of the layer and permits use of a selective etchant to remove all of the layer except the doped portion. The doped portion may then be used as a mask to define the base electrical contact, which in turn is used to provide a self-aligned base for the transistor. Dopants introduced on opposite sides of the base electrical contact create the emitter and collector.