Abstract: In a microprocessor having independent address and data paths and other pipeline architecture features, a control unit utilizes a PLA which stores microcoded instruction sequences. These sequences permit an operator at a console to read data from and write data to all the internal registers, any external memory location or the program counter. In addition, the PLA contains microcode which enables programs in external memory to be loaded from any location in memory and run by command from the console as well as to enable the operator to halt user program execution, read the pertinent internal registers, and then continue program execution such that single step execution for debug purposes is possible.

Abstract: In a capacitive storage integrated circuit dynamic random access memory having a cross-coupled transistor sense amplifier coupled to a bit line wherein capacitive storage cells are coupled to the bit line through transistor transfer gates, means are provided for restoring charge on the capacitive storage cell by recharging the memory cells directly rather than through the bit lines. Specifically, each storage cell has one terminal coupled to one electrode terminal of the transistor transfer gate and its other terminal coupled to a switched voltage reference. The storage cell is not referenced to a fixed ground level.

Abstract: Circuitry for rapidly discharging a row of RAM cells upon deselection of the word line. The word line switching transistor collector current is sensed and corresponding voltage level signals are applied to a second switching transistor between the bottom word line of the memory row and a large dump current source. The emitter of the second switching transistor is clamped at a level that will permit the switching transistor to turn on only when there is no emitter current through the word line switching transistor to thereby rapidly discharge the capacitive row of memory cells and therefore improve the operating speed of the memory.

Abstract: A power transistor array integrated circuit includes an array of transistors, each having an electrode connected in common to a conductive line forming a part of the integrated circuit. The electrodes of the transistors are spaced along the conductive line and have a decreasing length in a given direction along the conductive line and have a decreasing length in a given direction along the conductive line. The conductive line has a corresponding increasing width in the given direction. The decrease in length of the electrode and the increase in width of the conductive line are such that the electrodes and the conductive line form a generally rectangular shape. Differences in turn-on voltage for the transistors resulting from the differences in their electrode length tend to compensate for voltage drop in the conductive line, thus giving uniform outputs from the transistors in the array.

Abstract: A vertical bipolar transistor is fabricated in a semiconductor substrate without an epitaxial layer using oxide isolation and ion implantation techniques. Ion implantation energies in the KEV ranges are used to implant selected ions into the substrate to form a collector region and buried collector layer less than 1 micron from the surface of the device, and then to form a base region of opposite conductivity type in the collector layer and an emitter region of the first conductivity type in the base region. Even though ion implantation techniques are used to form all regions, the base and the emitter regions can, if desired, be formed to abut the field oxide used to laterally define the islands of semiconductor material. The field oxide is formed to a thickness of less than 1 micron and typically to a thickness of approximately 0.

Abstract: Phosphorus-doped silicon oxide glass is flowed on an integrated circuit by raising the pressure in which that integrated circuit is placed above atmospheric for a selected period of time and heating said phosphosilicate glass to a selected temperature sufficient to cause said glass to flow at said pressure. The atmosphere in which the device is placed includes moisture to enhance the flow of the glass at temperatures substantially beneath those at which dopants in the underlying integrated circuit move. The result is that the electrical characteristics of the integrated circuit are not substantially altered during glass flow.

Abstract: An improved lift-off process for forming metallized interconnections between various regions on a semi-conductor device relies on the use of a particular polyimide in forming a protective mask over the device. The polyimide is a copolymer of an aromatic cycloaliphatic diamine and a dianhydride which allows the resulting structure to withstand particularly high temperatures in the fabrication process. In particular, the polyamide when subjected to high temperature metallization under vacuum remains sufficiently soluble to be substantially completely removed from the device by immersion in common organic solvents. This allows high temperature metallization as interconnects for integrated circuits.

Abstract: A serpentine charge transfer device is disclosed in which two parallel series of charge transfer wells are disposed adjacent to each other. Channel stops and electrically controllable barriers are suitably introduced into the two series to cause charge to flow in a serpentine fashion along the two series of charge transfer wells. The invention doubles the resolution of linear imaging devices.

Abstract: A bit line powered translinear memory cell includes a pair of NPN transistors Q101 and Q102 having cross-coupled bases and collectors. Diode loads D101 and D102 couple the NPN transistors Q101 and Q102 to the bit lines 301 and 302. The emitters of the two transistors Q101 and Q102 are coupled together and to a word line 103. Cell parasitic capacitances C101 and C102 are used to maintain data in nonaddressed memory cells during reading of other cells coupled to the same word line 103.

Abstract: A process is provided for fabricating self-aligned contacts to the surface of an integrated circuit. The process includes the steps of depositing a layer of silicon dioxide 12 on the surface of a semiconductor structure 10; depositing a layer of polyimide 15 on the surface of the silicon dioxide 12; defining openings 23 in the polyimide material 15 and the silicon dioxide 12 to thereby expose regions of the semiconductor structure 10; and depositing metal 22 across the underlying surface and in the openings 23. In the preferred embodiment metal 22 is substantially the same thickness as silicon dioxide 12, and polyimide material 15 is masked using sequentially deposited layers of silicon dioxide 18 and photoresist 21.

Abstract: A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

Abstract: A method for encoding binary data into an electrically erasable memory. The memory includes a matrix of memory cells formed as a plurality of rows (X write lines/X sense lines/source lines) and columns (Y sense lines) with each cell including a floating gate field effect PMOS transistor and an NPN bipolar transistor. The method includes applying an erase voltage, e.g. +20 volts, to each of the Y sense lines while maintaining each of the X sense lines at this erase voltage and each of the X write lines at ground and applying the erase voltage to each of the source lines such that each of the PMOS transistors assumes a relatively negative threshold state. The method includes applying a write voltage e.g., +20 volts, to selected X write lines while maintaining unselected X write and selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage e.g., +10 volts, which is less than the write voltage, and maintaining each of the X sense lines at an intermediate voltage e.g.

Abstract: A lateral bipolar transistor having a base width of 0.

Abstract: In a method for welding a lead wire or bonding wire from a microcircuit chip mounted on a lead frame to a lead frame finger, the lead frame finger is preheated prior to any substantial electrical or thermal coupling between the lead frame finger and chip. Intense but controlled energy is applied to the lead frame finger at levels which might otherwise damage the IC chip. In one embodiment the lead frame finger is preheated to a temperature below the melting point of the metal comprising the lead frame. Enhanced bonding is thereafter effected by thermocompression bonding etc. In another embodiment the preheating step comprises melting a portion of the surface of the lead frame finger, forming a molten pool or puddle in the surface. Bonding of the lead wire is effected by immersing a section of the wire in the molten pool or puddle. In order to preheat the lead frame finger a controlled pulse train is delivered for arc discharge at the bonding location.

Abstract: A semiconductor structure is fabricated using a process involving all ion implantation and using only five masks prior to metallization. A buried contact mask is used to form a buried contact layer (114), an isolation mask is used to form grooves (130a, 130b) in an epitaxial layer of silicon (113), a self-aligned transistor mask is used to form a mask (134a to 134e) to define the areas in which emitters (138a, 140b, 140c) bases (113, 139) and contact regions (140a) are to be formed, a base exclusion mask (135a,b) is provided to exclude certain impurities from being implanted into a region to be formed of one conductivity type, and a second exclusion mask (137a, 137b) is provided to exclude impurities to be implanted in a region of opposite conductivity type from the prohibited regions of the structure.

Abstract: In a digital tester for evaluating electronic components, a local memory unit for each data channel in the tester is loaded with test vector information only in the locations of the memory relating to transitions that take place in the operation of the data channel. In addition, a transition bit is stored in each memory location to signify whether the vector information in that location represents valid transition data. The transition bit is used to control the reading of information from the memory into a register that controls the flow of information in the data channel, so that only the valid transition vectors are fed into data channel control circuitry. This procedure substantially reduces the amount of data that must be loaded into the memory, and hence reduces the total time necessary to thoroughly test a circuit.

Abstract: In a semiconductor device, laser energy is used to selectively heat various SiO.sub.2 and/or GeO.sub.2 based materials to elevated temperatures while maintaining the active device region and electrical interconnects at relatively low temperatures, to for example, induce densification and/or flow of the SiO.sub.2 and/or GeO.sub.2 based material to round off sharp edges and stops, without damaging or affecting the active region and electrical interconnects.

Abstract: A process is described for removing polyimide regions adhered to the surface of a semiconductor structure 10 which includes the steps of heating the structure 10 and the polyimide regions 12 to between 450.degree. and 490.degree. C., immersing the structure in a solution of one of methylene chloride and ethylene diamine/hydrazine, and ultrasonerating the solution and the semiconductor structure.

Abstract: A process and structure are disclosed which are suitable for forming large arrays of Schottky diodes at desired locations between mutually perpendicular strips of aluminum and strips of metal-silicide. The invention is particularly useful in creating read-only memories and programmable logic arrays, and allows fabrication of Schottky diodes more compactly than previous structures.

Abstract: A novel process is disclosed for the selective etching of a protective layer over a substrate according to a predetermined pattern, which does not involve the use of chemical vapor deposition or vacuum techniques. The process incorporates the techniques of electroless metal deposition after first applying a mask which is positive with respect to the predetermined pattern. In alternative embodiments, the application to the masked protective layer of an agent catalytic to the reception of electroless metal deposition is followed by either immersion in an electroless plating bath and subsequent mask removal, or by mask removal and subsequent immersion in the electroless plating bath. In either embodiment, the protective layer is effectively masked and patterned for plasma etching. The process is useful in forming openings in the protective layer to permit selective doping of the underlying substrate.