Abstract: A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the bases and collectors of the two transistors Q1 and Q2 forming the memory cell. The metal silicide 30 shorts PN junctions 29 in polycrystalline 23. Two further strips 50 and 52, each comprising a sandwich of P type polycrystalline silicon 42, metal silicide 45, and N conductivity type polycrystalline silicon 47, are formed to couple the cross-coupled bases and collectors to respective diodes 60 and 65. The diodes 60 and 65 are formed by depositing metal 62 and 64 in electrical contact with the underlying N type polycrystalline silicon 47.

Abstract: A tunable CO.sub.2 gas laser is used to selectively heat various SiO.sub.2 -based materials to elevated temperatures while maintaining an active device region at relatively low temperatures, to, for example, induce densification and/or flow of the SiO.sub.2 -based material to round off sharp edges and stops.

Abstract: A silicon substrate having a silicon dioxide bird's head is provided. A thermal oxide layer is grown on the exposed silicon surface. A layer, e.g., 4000 A.degree., of phosphogermanosilicate glass is deposited on the thermal oxide and on the silicon dioxide bird's head. The structure is heated to 950.degree. C., causing a reflow of the glass which results in a planar surface. The thermal oxide and the phosphogermanosilicate glass are then wet etched at the same rate with a solution of hydrofluoric acid, ammonium fluoride, and deionized water. The wet etch is terminated when the exposed silicon surface is reached, resulting in a smooth surface as defined by the planar reflow surface. Other embodiments are disclosed.

Abstract: A digital and linear dynamic ignition control apparatus comprising a burn-time counter, a pre-dwell counter, a current limit counter, engine speed detection apparatus, a biasing circuit and an excess current limit circuit is provided for controlling the start of a dwell in each ignition period. In operation, a current limit adjust window is established for each period. The time of the termination of a dwell in the period relative to the current limit adjust window established for the period starts the dwell in the next period relative to the beginning of the next period at a time calculated to optimize engine performance and minimize energy losses. In general, rapid acceleration in a period starts the dwell earlier in the next period to insure adequate charging of the ignition coil. Conversely, rapid deceleration in a period starts the dwell later in the next period to minimize energy losses.

Abstract: Speech and like signals are analyzed based on a model of the function of the human hearing system. The model of the inner ear is expressed as signal processing operations which map acoustic signals into neural representations. Specifically, a high order transfer function is modeled as a cascade/parallel filterbank network of simple linear, time-invariant second-order filter sections. Signal transduction and compression are based on a half-wave rectification with a non-linearly coupled, variable time constant automatic gain control network. The result is a simple device which simulates the complex signal transfer function associated with the human ear. The invention lends itself to implementation in digital circuitry for real-time or near real-time processing of speech and other sounds.

Abstract: Method and apparatus are provided for measuring the settling time, relative to a reference time, of an analog signal having a varying amplitude. The apparatus includes a pair of comparators U1 and U2 for comparing the amplitude of the analog signal with first and second reference signals V.sub.Ref 1 and V.sub.Ref 2. The comparators U1 and U2 are connected to edge detector 22 which supplies a reset signal to a second counter 26 whenever the amplitude of the analog signal is not between the first and second reference signals. Oscillator 32 drives counters 25 and 26 which count pulses from oscillator beginning at the reference time and continuing until the second counter 26 contains a predetermined count. Because the second counter 26 is reset by the edge detector 22 whenever the analog waveform exceeds either of the reference signals, the difference between counter 25 and counter 26 at any subsequent time after the waveform has settled will be the settling time of the analog waveform.

Abstract: A digital comparator for determining whether a digital test signal qualifies as an expected logic level, particularly suited to in-circuit digital testing applications. First and second comparing circuits, each formed by a differential amplifier circuit, receive the test signal, a high threshold signal and a low threshold signal. A control circuit selectively enables and inhibits the two comparing circuits so that only one is operative at any instant depending on the expected level of the test signal. The output terminals of the comparing circuits are connected so that the enabled one of the comparing circuits directly provides a pass/fail indication. A standby circuit allows both comparing circuits simultaneously to be selectively energized or deenergized, and an input buffer circuit permits the selective variation of the input impedance of the comparing circuit on the basis of the type of test being performed.

Abstract: A process is disclosed for fabricating complementary n and p channel insulated gate field effect transistors. The process uses two layers of polycrystalline silicon 32 and 44 to provide electrical interconnections, and allows the formation of microcapacitors between the two layers of polycrystalline silicon. In addition silicon dioxide and silicon nitride, and two layers of photoresist, are used as masks against heavy boron implantations. The reliability of ohmic connections between aluminum 50 and contact regions in the substrate is enhanced by providing additional dopant to the contact regions. In this way, the junction depth is increased and electrical defects caused by metal spiking are minimized.

Abstract: During the in-circuit testing of electronic components, stimulus pulses are applied to a circuit bus producing an improper output signal, and the response of the circuit at various nodes connected to the bus is sensed with a current probe. An output signal from the current probe that is indicative of the magnitude and relative direction of the sensed current is sampled during each of the stimulus pulses to thereby isolate the portion of the output signal relating to the pulses from any noise in the circuit being tested. The sampled signal is further integrated to provide an additional measure of isolation, so that the probe signal processing circuit is relatively insensitive to both constant, high frequency noise and random, irregular or low frequency noise components.

Abstract: A process is described for fabricating spacers of a desired thickness of filters, the spacers to be used in separating the filter from an underlying image sensing device. The process includes the steps of forming a pattern of electrically conductive material on one surface of the filter, depositing dry resist to the desired thickness over all of the filter except on the electrically conductive pattern, depositing additional electrically conductive material on at least the electrically conductive pattern, and removing the dry resist.

Abstract: Base resistance in an integrated injection logic cell is reduced by providing a low resistance conductive path over the device cell and contacting the base regions of vertical transistors in the cell. In fabricating the I.sup.2 L cell a first intrinsic polysilicon layer is formed over the surface of the device cell, and N-type dopant is diffused through the polysilicon layer to form the N+ collectors of the NPN vertical transistors. Silicon oxide is formed over the doped polysilicon and the undoped intrinsic polysilicon is then removed. Exposed edge portions of the N doped polysilicon is then oxidized to completely insulate the surface of the polysilicon. A second layer of intrinsic polysilicon is then formed over the device cell and P type dopant is diffused through the second polysilicon layer to form the emitter and collector of a lateral PNP transistor and to contact the base regions of the NPN vertical transistors between the N+ collectors.

Abstract: Apparatus is provided for supplying deskewed signals. The apparatus includes a timing generator (20) for generating a pulse of desired duration, a deskew unit (17) connected to receive a pulse and adjust its width to compensate for previous errors, a differentiation network (15) for dividing the pulse into a leading and trailing edge signal, a plurality of logic gates (80 through 85) for receiving the pair of signals and supplying one of the pair along a set path and the other of the pair along a reset path, a deskew unit (86 and 89) associated with each path for delaying the signals thereon, and a latch (53) coupled to the deskew units to reform the electrical signal. Logic gates (80 through 85) operate under control of a format selector (90).

Abstract: A method for fabricating a semiconductor structure which reduces substrate current injection from lateral bipolar transistors. A buried layer of a first conductivity type is formed in a semiconductor substrate of opposite conductivity. An epitaxial layer of the first conductivity type is formed such that at least a portion of the epitaxial layer overlies the buried layer. Isolation oxide regions are formed in a epitaxial layer. The isolation oxide regions extend to the substrate to define an island of electrically isolated epitaxial material. A selected impurity of the first conductivity type is introduced into that portion of the epitaxial layer beneath the to-be-formed lateral transistor. The lateral transistor is formed in the epitaxial layer.

Abstract: A power MOSFET semiconductor structure is fabricated using the steps of depositing an epitaxial layer 12 of N conductivity type silicon on an underlying silicon substrate 10 of N conductivity type, forming a plurality of polycrystalline silicon electrodes 18 on the epitaxial layer 12, each electrode 18 being separated from the epitaxial layer 12 by a layer of insulating material 15; introducing P 30 and N 33 conductivity type impurities into the epitaxial layer 12 between the electrodes 18, the P type impurity 30 underlying the N type impurity 33; removing regions of the epitaxial layer 12 to form openings 21 in the epitaxial layer 12 between the electrodes 18, the removed regions 21 extending through the N type region 33 but not through the P type region 30; and depositing electrically conductive material 40 in the opening 23.

Abstract: A process of fabricating a polycrystalline silicon resistor on a semiconductor structure is disclosed. According to the process insulating material is fabricated over selected regions of the semiconductor structure 10, and selected impurity 18 introduced into the insulating material, typically in conjunction with other process operations useful in fabricating semiconductor structures. Undoped regions of polycrystalline silicon 21 are then formed on the surface of the insulating material 15 and the entire structure is treated to cause the dopant in the insulating material 15 to out diffuse into the undoped polycrystalline silicon to thereby create resistors. The treating operation is typically the heat treatment performed in conjunction with other process operations in the fabrication of integrated circuits.

Abstract: A test system memory architecture for passing parameters and testing dynamic components includes a main memory 15, a mask memory 20, and a definition memory 25, operating under control of a main sequence control memory 18. A corresponding subroutine memory 38, subroutine mask memory 22, and subroutine definition memory 27 operate under control of a subroutine sequence control memory 33. Multiplexing apparatus is used to selectively connect any of these memories to the formatter circuit 10. In addition, the architecture includes a parameter enabling memory 30 which is coupled to the subroutine SCM 33 and a switching means for controlling which of the subroutine memory 38 or main memory 15 is coupled to the formatter circuit 10.

Abstract: Manufacture of bipolar substantially isoplanar integrated circuit structures is accomplished by rearrangement of the conventional masking steps and by the substitution and full integration of implanting methods for diffusion methods. A uniform nitride layer is deposited over the basic structure of epitaxial islands separated by isolation oxide regions thereby passivating and protecting the isolation oxide regions, epitaxial oxide buffer layer and epitaxial layer from environmental contaminants. The nitride layer which forms part of a composite protective layer is maintained in place throughout a major portion of the fully integrated sequential implanting steps during which the collector sink, base and emitter regions are introduced into the epitaxial islands. At least a portion of the composite protective layer is a barrier to environmental contaminants throughout the process. The overall number of steps is reduced, etching steps minimized, and overall reliability of the structure improved.

Abstract: An apparatus is described for maintaining and delivering a slack reserve length of lead wire between a spool or other source and the wire bonding tool of a lead wire bonding machine. A slack chamber or wind chamber comprised of a housing enclosure, an inlet guide on one side for guiding lead wire into the slack chamber from a spool, an outlet guide on the other side for guiding lead wire out of the slack chamber towards the wire bonding tool maintains the reserve length of lead wire in untangled condition. A source of pressurized dry air or other gas directs a gaseous flow into the slack chamber so that the lead wire is maintained suspended in the gaseous flow in an offset configuration. Wire sensors are operatively positioned in the slack chamber for sensing the offset of lead wire in the wind stream. The wire sensors are coupled to sensor and control logic for controlling the delivery and feeding of lead wire from a spool into the slack chamber.

Abstract: This invention provides a single integrated circuit device which replaces the non-integrated "encapsulated circuit" of the standard prior art telephone set. The circuit of this invention achieves proper D.C. regulation of the telephone line, by presenting one of several possible D.C. impedances to the telephone line when the telephone set is in the off-hook condition. The circuit of this device provides such regulation by varying the gain relationship of the telephone set for various distances from the central switching office, thereby maintaining a rather uniform signal amplitude in a plurality of telephone sets located at various distances from the central switching office. In one embodiment, this is done using a novel regulator substantially completely formed as part of a single integrated circuit chip containing a receiver amplifier, transmitting amplifier, dialing circuitry and ringing circuitry.

Abstract: A method, timing control circuit, and power supply are described for initiating arc discharge between the cover gas delivery shroud and lead wire held in the bonding tool of a lead wire bonding machine for melting and forming a ball at the end of the lead wire. An arc discharge timing control pulse controls duration of the arc discharge within an empirically determined time window between the shortest and longest durations of arc discharge which result in optimal ball formation of a substantially spherical ball at the end of the lead wire without necking of the lead wire above the formed ball. The timing control circuit also provides an initial cover gas movement delay before ball formation for displacing oxygen from the shield and the end of the lead wire, and a subsequent cooling delay for solidifying and cooling the formed ball in the cover gas stream prior to ball bonding.