Abstract: A processor controlled IC component test apparatus adapted to be employed in-line with automatic IC DIP component handling equipment is capable of conducting a preselected verification check of each IC device regardless of the orientation of the DIP in the device contact receptable of the IC handling apparatus. As each device under test (DUT) is inserted into the apparatus test head, a pin-check residual voltage measurement test is conducted to ensure that all the pins of the DUT are in contact with the contact terminals of the test head. If the pin-check test establishes that all the pins of the DUT are in contact with the contact terminals of the test head, a prescribed non-destructive impedance measurement test is carried out in order to determine the orientation of the DIP in the test head.

Abstract: An electrically erasable programmable read-only memory (E.sup.2 PROM) is provided which utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows. In the preferred embodiment, each memory cell of the E.sup.2 PROM array consists of a single floating gate field effect transistor. The E.sup.2 PROM of the present invention provides for row erasure and single bit writing.

Abstract: The lateral spacing between buried regions separated by oxide-isolation regions in a semiconductor structure is reduced to as little as one micron by performing a deep implantation of ions of the conductivity type opposite to that of the buried regions generally into portions of the substrate below the sites where the oxide-isolation regions are formed.