Patents Assigned to Fairchild Camera & Instrument
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Patent number: 5166094Abstract: A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.Type: GrantFiled: June 18, 1990Date of Patent: November 24, 1992Assignee: Fairchild Camera & Instrument Corp.Inventor: Ashok K. Kapoor
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Patent number: 4947230Abstract: A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in a required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.Type: GrantFiled: September 14, 1984Date of Patent: August 7, 1990Assignee: Fairchild Camera & Instrument Corp.Inventor: Ashok K. Kapoor
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Patent number: 4918506Abstract: A line scan image sensor capable of operating at several different spatial sampling frequencies is provided by utilizing a line scanning array having sampling photoelements of different surface areas. The spatial sampling frequency of the sensor can be varied by selectively combining the charge packets generated by the individual photoelements. In a preferred embodiment, photoelements having two different surface areas are used, with the ratio of the smaller surface area with respect to the larger surface area being 1:.sqroot.2. A programmable amplifier is provided to normalize the outputs of photoelements having different surface areas so that a uniform illumination on different photoelements will produce a uniform response. The programmable amplifier can also be programmed to equalize the outputs of the sensor between the different spatial sampling frequency modes.Type: GrantFiled: September 13, 1985Date of Patent: April 17, 1990Assignee: Fairchild Camera & Instrument CorporationInventor: Rudolph H. Dyck
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Patent number: 4833521Abstract: A method and means for reducing signal propagation losses in very large scale integrated circuits is provided comprising a ground plane located adjacent to, but insulated from, a conductive signal layer overlying an active region in a semiconductor substrate. While, the ground plane is preferrably disposed between the signal layer and the substrate, it may be disposed above the signal layer. Moreover, two or more signal layers may be employed and sandwiched between a pair of ground planes.Type: GrantFiled: July 8, 1988Date of Patent: May 23, 1989Assignee: Fairchild Camera & Instrument Corp.Inventor: James M. Early
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Patent number: 4789835Abstract: A system which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information related to a base time delay, while a vernier memory stores information relating to timing corrections to be made to the base time delay. The base delay memory controls a counter while the correction memory controls a vernier deskew apparatus for further delaying the output signal from the counter. To prevent carries from the vernier memory from influencing the base delay memory, the most significant bit of the vernier memory is of the same significance as the least significant bit of the base delay memory. The most significant bit of the vernier memory is also connected to drive the counter, in effect providing the counter with two least significant bits, and enabling a single base delay memory to control more than one signal timing paths.Type: GrantFiled: July 2, 1987Date of Patent: December 6, 1988Assignee: Fairchild Camera & Instrument CorporationInventor: Richard F. Herlein
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Patent number: 4764925Abstract: A processor controlled IC component test apparatus adapted to be employed in-line with automatic IC DIP component handling equipment is capable of conducting a preselected verification check of each IC device regardless of the orientation of the DIP in the device contact receptable of the IC handling apparatus. As each device under test (DUT) is inserted into the apparatus test head, a pin-check residual voltage measurement test is conducted to ensure that all the pins of the DUT are in contact with the contact terminals of the test head. If the pin-check test establishes that all the pins of the DUT are in contact with the contact terminals of the test head, a prescribed non-destructive impedance measurement test is carried out in order to determine the orientation of the DIP in the test head.Type: GrantFiled: June 14, 1984Date of Patent: August 16, 1988Assignee: Fairchild Camera & InstrumentInventors: Scott D. Grimes, Lary J. Beaulieu, Douglas A. Reed
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Patent number: 4742551Abstract: A subsystem component for use in an image processing system to compute a gray scale histogram function or various statistical functions relating to the coordinates of a region or regions in a binary image. A selected function is computed at the video rate of frame generation.Type: GrantFiled: October 7, 1985Date of Patent: May 3, 1988Assignee: Fairchild Camera & Instrument CorporationInventor: Michael F. Deering
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Patent number: 4740776Abstract: A high precision digital to analog converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compenate for errors of any bit combination. In a specific embodiment employing feedforward compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.Type: GrantFiled: October 14, 1983Date of Patent: April 26, 1988Assignee: Fairchild Camera & Instrument CorporationInventor: Edwin A. Sloane
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Patent number: 4727269Abstract: A temperature compensated sense amplifier is connected to the sense node of a memory array which is OR tied to the bit lines of the array. A PNP current mirror supplies voltage independent controlled current to the sense node. A level shifting stage is connected to the sense node to establish a threshold sensing level, and to switch on to steer the current into the amplifier stage. A compensation stage is connected to the level shifting stage and the amplifier stage to compensate for the .beta. factors of the transistors and the resistive changes with temperature. A temperature compensated current sink is connected to the PNP current mirror to track over temperature in opposition therewith and maintain a constant current into the sense node. The level shifting stage and the amplifier stage also include temperature compensating features to provide a sensing threshold which tracks constantly over the operating temperature range.Type: GrantFiled: August 15, 1985Date of Patent: February 23, 1988Assignee: Fairchild Camera & Instrument CorporationInventor: Thomas M. Luich
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Patent number: 4727048Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.Type: GrantFiled: October 2, 1986Date of Patent: February 23, 1988Assignee: Fairchild Camera & Instrument CorporationInventors: John M. Pierce, William I. Lehrer
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Patent number: 4713750Abstract: A microprocessor with a multiplexer having its output coupled to the input of the instruction register for storing instructions to be executed and applying the bits of the instruction as the input signals to a mapping PLA. The inputs of the multiplexer are the information bus coupled to external pins to receive instructions either from external memory or from an external console, and the output of the ALU. The path from the output of the ALU to the input of the instruction register allows better self testing of the processor by iteself and self-generation of input/output instructions. This structure simplifies the processor by allowing console requests, instructions from memory and self generated instructions all to be stored in the same register, i.e., the instruction register, thereby eliminating the need for separate registers for each type of instruction.Type: GrantFiled: October 30, 1984Date of Patent: December 15, 1987Assignee: Fairchild Camera & Instrument CorporationInventors: Nabil G. Damouny, Min-Siu Huang, Dan Wilnai, Yeshayahu Mor
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Patent number: 4712233Abstract: The present invention is an improved subscriber line interface circuit which allows fast detection of an off-hook signal in the presence of a ringing signal during an answer mode while also permitting fast detection of dialing pulses during a calling mode. A programmable filter is used in the supervision circuit of the SLIC to allow the cutoff frequency of the filter to be varied so that the 20 Hz ringing signal will be attenuated during a ringing sequence and dialing pulse rates up to 20 Hz will be passed by the filter during the calling mode. A clamping amplifier is used to clamp the received signal to a maximum of 1.5 times the loop threshold current. This eliminates the large variations in the rise and fall times of the pulse dialing signal due to variations in the loop current caused by varying impedances of the telephone line. The filter is programmed by using an analog switch to bypass certain filter elements.Type: GrantFiled: April 22, 1985Date of Patent: December 8, 1987Assignee: Fairchild Camera & Instrument Corp.Inventor: James R. Kuo
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Patent number: 4686628Abstract: A method and apparatus for testing an electrical device and/or circuit in which the device or circuit is stimulated with a known input signal and in which three or more measurements of the response of the device or circuit to such stimulus are taken and utilized to predict a final value of such response according to a predetermined relationship between such predicted final response and the measured response values. Typically the present invention can predict such final value without waiting for the actual final value of the response to occur.Type: GrantFiled: July 19, 1984Date of Patent: August 11, 1987Assignee: Fairchild Camera & Instrument Corp.Inventors: Keibock Lee, Robert V. Dvorak
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Patent number: 4654269Abstract: There is disclosed herein a stress relieved intermediate insulating layer consisting of one or more layers of spun-on glass lying over a metalization pattern. The spun-on layers are allowed to crack from thermal stress imposed upon the structure. The cracks in the spun-on layers are then filled with a glass layer deposited by CVD or LPCVD.Type: GrantFiled: June 21, 1985Date of Patent: March 31, 1987Assignee: Fairchild Camera & Instrument Corp.Inventor: William I. Lehrer
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Patent number: 4651038Abstract: A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent.Type: GrantFiled: May 17, 1984Date of Patent: March 17, 1987Assignee: Fairchild Camera & Instrument CorporationInventors: Ronald L. Cline, John G. Campbell
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Patent number: 4640004Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.Type: GrantFiled: April 13, 1984Date of Patent: February 3, 1987Assignee: Fairchild Camera & Instrument Corp.Inventors: Michael E. Thomas, Madhukar B. Vora, Ashok K. Kapoor
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Patent number: 4630343Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.Type: GrantFiled: September 6, 1985Date of Patent: December 23, 1986Assignee: Fairchild Camera & Instrument Corp.Inventors: John M. Pierce, William I. Lehrer
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Patent number: 4624046Abstract: An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by elminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacutre PROMS from vertical NPN transistors. An LV.sub.Type: GrantFiled: August 27, 1985Date of Patent: November 25, 1986Assignee: Fairchild Camera & Instrument Corp.Inventors: Jay A. Shideler, Umeshwar D. Mishra
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Patent number: 4619844Abstract: A method of introducing a controlled flow of vapor from a high pressure sublimation chamber into a low pressure vapor deposition reactor, said vapor being derived from solid source material preferably, but not necessarily, having a vapor pressure above about one (1) Torr at a temperature not exceeding about 350.degree. C. The method comprises controllably heating the source material to a temperature sufficient to produce vapor therefrom at a desired pressure, and then controllably transferring the vapor through vapor transmission means to the vapor deposition reactor. During such transfer, the transmission means is maintained at a temperature sufficient to prevent condensation of the vapor therein during transfer. The vapor is delivered to the reactor in a pure state and is not mixed with any carrier medium.Type: GrantFiled: January 22, 1985Date of Patent: October 28, 1986Assignee: Fairchild Camera Instrument Corp.Inventors: John M. Pierce, William I. Lehrer
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Patent number: 4619839Abstract: A method for forming a substantially planar inorganic dielectric layer over a predetermined pattern of electrical interconnects comprises the steps of reacting phosphoric acid and a trivalent metallic halide compound with an aliphatic solvent to form a coating fluid. The coating fluid is then spun onto the semiconductor device to form a layer over the electrical interconnect. The resultant device is then baked at a first temperature to drive off the solvent and then baked at a second, higher temperature, in order to promote the glass forming reaction. This process is repeated as required to form a coating layer having a thickness which exhibits levelling characteristics of such high quality that fine topography can be carried out on succeeding layers of metal in order to form additional interconnect layers with precision.Type: GrantFiled: December 12, 1984Date of Patent: October 28, 1986Assignee: Fairchild Camera & Instrument Corp.Inventor: William I. Lehrer