Abstract: A digital and linear dynamic ignition control apparatus comprising a burn-time counter, a pre-dwell counter, a current limit counter, engine speed detection apparatus, a biasing circuit and an excess current limit circuit is provided for controlling the start of a dwell in each ignition period. In operation, a current limit adjust window is established for each period. The time of the termination of a dwell in the period relative to the current limit adjust window established for the period starts the dwell in the next period relative to the beginning of the next period at a time calculated to optimize engine performance and minimize energy losses. In general, rapid acceleration in a period starts the dwell earlier in the next period to insure adequate charging of the ignition coil. Conversely, rapid deceleration in a period starts the dwell later in the next period to minimize energy losses.

Abstract: A novel zero insertion (and removal) force multi-pin coaxial connector for providing connections via controlled impedance paths is formed using a conductive elastomer as a frame (8) which forms the shield of a plurality of coaxial connectors and a plurality of circular openings formed in the conductive elastomer frame, each said opening corresponding to a single coaxial connection. An annular insulating ring (5), which forms the dielectric of an associated one of the coaxial connectors, is located in each annular opening of the conductive elastomer frame and an elastomer through-conductive member (6) which forms the center conductor of its associated coaxial connector is located within the circular opening of each insulating ring. In this manner, the conductive elastomer frame forms the shield of a plurality of coaxial connectors.

Abstract: A process is disclosed for fabricating complementary n and p channel insulated gate field effect transistors. The process uses two layers of polycrystalline silicon 32 and 44 to provide electrical interconnections, and allows the formation of microcapacitors between the two layers of polycrystalline silicon. In addition silicon dioxide and silicon nitride, and two layers of photoresist, are used as masks against heavy boron implantations. The reliability of ohmic connections between aluminum 50 and contact regions in the substrate is enhanced by providing additional dopant to the contact regions. In this way, the junction depth is increased and electrical defects caused by metal spiking are minimized.

Abstract: A process is described for fabricating spacers of a desired thickness of filters, the spacers to be used in separating the filter from an underlying image sensing device. The process includes the steps of forming a pattern of electrically conductive material on one surface of the filter, depositing dry resist to the desired thickness over all of the filter except on the electrically conductive pattern, depositing additional electrically conductive material on at least the electrically conductive pattern, and removing the dry resist.

Abstract: Base resistance in an integrated injection logic cell is reduced by providing a low resistance conductive path over the device cell and contacting the base regions of vertical transistors in the cell. In fabricating the I.sup.2 L cell a first intrinsic polysilicon layer is formed over the surface of the device cell, and N-type dopant is diffused through the polysilicon layer to form the N+ collectors of the NPN vertical transistors. Silicon oxide is formed over the doped polysilicon and the undoped intrinsic polysilicon is then removed. Exposed edge portions of the N doped polysilicon is then oxidized to completely insulate the surface of the polysilicon. A second layer of intrinsic polysilicon is then formed over the device cell and P type dopant is diffused through the second polysilicon layer to form the emitter and collector of a lateral PNP transistor and to contact the base regions of the NPN vertical transistors between the N+ collectors.

Abstract: A method for fabricating a semiconductor structure which reduces substrate current injection from lateral bipolar transistors. A buried layer of a first conductivity type is formed in a semiconductor substrate of opposite conductivity. An epitaxial layer of the first conductivity type is formed such that at least a portion of the epitaxial layer overlies the buried layer. Isolation oxide regions are formed in a epitaxial layer. The isolation oxide regions extend to the substrate to define an island of electrically isolated epitaxial material. A selected impurity of the first conductivity type is introduced into that portion of the epitaxial layer beneath the to-be-formed lateral transistor. The lateral transistor is formed in the epitaxial layer.

Abstract: A power MOSFET semiconductor structure is fabricated using the steps of depositing an epitaxial layer 12 of N conductivity type silicon on an underlying silicon substrate 10 of N conductivity type, forming a plurality of polycrystalline silicon electrodes 18 on the epitaxial layer 12, each electrode 18 being separated from the epitaxial layer 12 by a layer of insulating material 15; introducing P 30 and N 33 conductivity type impurities into the epitaxial layer 12 between the electrodes 18, the P type impurity 30 underlying the N type impurity 33; removing regions of the epitaxial layer 12 to form openings 21 in the epitaxial layer 12 between the electrodes 18, the removed regions 21 extending through the N type region 33 but not through the P type region 30; and depositing electrically conductive material 40 in the opening 23.

Abstract: A process of fabricating a polycrystalline silicon resistor on a semiconductor structure is disclosed. According to the process insulating material is fabricated over selected regions of the semiconductor structure 10, and selected impurity 18 introduced into the insulating material, typically in conjunction with other process operations useful in fabricating semiconductor structures. Undoped regions of polycrystalline silicon 21 are then formed on the surface of the insulating material 15 and the entire structure is treated to cause the dopant in the insulating material 15 to out diffuse into the undoped polycrystalline silicon to thereby create resistors. The treating operation is typically the heat treatment performed in conjunction with other process operations in the fabrication of integrated circuits.

Abstract: Manufacture of bipolar substantially isoplanar integrated circuit structures is accomplished by rearrangement of the conventional masking steps and by the substitution and full integration of implanting methods for diffusion methods. A uniform nitride layer is deposited over the basic structure of epitaxial islands separated by isolation oxide regions thereby passivating and protecting the isolation oxide regions, epitaxial oxide buffer layer and epitaxial layer from environmental contaminants. The nitride layer which forms part of a composite protective layer is maintained in place throughout a major portion of the fully integrated sequential implanting steps during which the collector sink, base and emitter regions are introduced into the epitaxial islands. At least a portion of the composite protective layer is a barrier to environmental contaminants throughout the process. The overall number of steps is reduced, etching steps minimized, and overall reliability of the structure improved.

Abstract: An apparatus is described for maintaining and delivering a slack reserve length of lead wire between a spool or other source and the wire bonding tool of a lead wire bonding machine. A slack chamber or wind chamber comprised of a housing enclosure, an inlet guide on one side for guiding lead wire into the slack chamber from a spool, an outlet guide on the other side for guiding lead wire out of the slack chamber towards the wire bonding tool maintains the reserve length of lead wire in untangled condition. A source of pressurized dry air or other gas directs a gaseous flow into the slack chamber so that the lead wire is maintained suspended in the gaseous flow in an offset configuration. Wire sensors are operatively positioned in the slack chamber for sensing the offset of lead wire in the wind stream. The wire sensors are coupled to sensor and control logic for controlling the delivery and feeding of lead wire from a spool into the slack chamber.

Abstract: An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

Abstract: A data channel for a digital tester includes a random access local memory containing a main vector sequence, a subroutine vector sequence, and a test vector list. An index register is loaded with the address of the first vector in the list of vectors that is to be inserted as a variable into a vector stream. A sequence instruction selects the index register as the source of a test vector address when a variable vector is to be inserted into the vector stream at a point in a subroutine. The sequence instruction also resets the index register to a state which determines the address of the next variable to be inserted into the test vector pattern.

Abstract: A method and system for loading test data into individual pin memories of an automatic digital test system, particularly of the in-circuit type. Test data in the form of test vectors are accessed from a test vector store simultaneously with the access of a digital test pin selection signal. The test pin selection signal accessed with the test data is then used to selectively load the test data into a pin memory identified by the pin selection signal, thereby permitting the loading of test data into any one of a group of individual pin memories. In the preferrred embodiment the test data, a test vector, is stored in a test vector store in association with a test pin selection signal. When the test vector is read from memory, the test pin selection signal is also read by the same address signal.

Abstract: A low temperature insulating glass for use in semiconductor devices comprises a mixture of germanium, silicon, oxygen and phosphorus. In the preferred embodiment, the glass comprises a mixture of about 40% to 55% silicon dioxide (SiO.sub.2), about 55% to 40% of germanium dioxide (GeO.sub.2) and from 1% to about 5% of phosphorus pentoxide (P.sub.2 O.sub.5), by mole percent.

Abstract: A method for impregnating copper into aluminum interconnect lines on a semiconductor device is disclosed. In a first embodiment, an interconnect pattern is formed on an aluminum layer by etching while the aluminum is substantially free from copper, and the copper is thereafter introduced to the formed interconnect lines. In a second embodiment, copper is introduced to the aluminum layer prior to formation of the desired interconnect pattern. The copper-rich layer is removed from the areas to be etched prior to etching. The method facilitates chlorine plasma etching of the aluminum which is inhibited by the presence of copper. The method is also useful with various wet etching processes where the formation of a copper-rich layer is found to stabilize the aluminum layer during subsequent processing .

Abstract: A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PN junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

Abstract: A current bypass for a microelectric memory, such as a static RAM, diverts word line discharge current such that the current does not flow through the memory cells of a selected word line or along an upper word line conductor. In a first embodiment, the bypass comprises a resistor R1 (R2) and a diode D10 (D20) in series and coupled between an upper word line conductor 50 and word line discharge current source V.sub.CC, and a lower word line conductor 51 and word line discharge current sink 42. In another embodiment of the invention, a transistor Q10 (Q20) is used in lieu of the diode. By bypassing current from the upper word line conductor and word line memory cells, metal migration is eliminated and narrower metal lines may be used to form the word lines. By eliminating a flow of steady state discharge current through the memory cells, memory cell current saturation is eliminated.

Abstract: A process and resulting structure are disclosed for forming vias in integrated circuit structures using metal silicide interconnections. A lower conductor is formed by sequentially depositing silicon and a refractory metal which reacts with the silicon to create a layer of metal silicide. A subsequent layer of silicon is deposited on the surface of the metal silicide. This layer of silicon is insulated from overlying layers by forming insulating material over desired regions of the layer of silicon. A second layer of metal is then deposited across the structure. In openings in the insulating material the metal reacts with the second layer of silicon to form a via of metal silicide. A final layer of silicon may be deposited to convert any remaining metal in the second layer of metal to metal silicide, and the structure annealed to lower its resistivity.

Abstract: Apparatus is provided for substituting a spare column of memory cells in a byte wide memory for a defective column of cells in such memory. The apparatus includes a spare column of memory cells, an electrically conductive line 13, a spare decoder 16 for switchably connecting the line 13 to the spare column, a first fuse FSD.sub.1 between the spare column and the line 13, a series of second fuses FS controlling a series of switches T.sub.1, T.sub.2 . . . between the line 13 and corresponding sense amplifiers 11, and a series of third fuses FD, each connected between a corresponding column and the sense amplifier associated with that column. The spare column of memory cells is connected to the appropriate sense amplifier by blowing the appropriate fuse FS and supplying the necessary address information to spare decoder 16. The defective column of memory cells may be disconnected by blowing the appropriate fuse FD.

Abstract: The disclosure relates to techniques for etching layered materials to produce features with beveled edges, for example, wells in silicon oxide layers employed in integrated circuit fabrication. An anisotropic etch may be employed to form wells with vertical walls in the silicon oxide layer, and an isotropic etch may be employed to bevel peripheral corners of the walls. In preferred embodiments, a double mask of a photoresist layer on an underlying thin film may be used to define the limits of the anisotropic and isotropic etches, respectively.