Abstract: An apparatus is described for maintaining and delivering a slack reserve length of lead wire between a spool or other source and the wire bonding tool of a lead wire bonding machine. A slack chamber or wind chamber comprised of a housing enclosure, an inlet guide on one side for guiding lead wire into the slack chamber from a spool, an outlet guide on the other side for guiding lead wire out of the slack chamber towards the wire bonding tool maintains the reserve length of lead wire in untangled condition. A source of pressurized dry air or other gas directs a gaseous flow into the slack chamber so that the lead wire is maintained suspended in the gaseous flow in an offset configuration. Wire sensors are operatively positioned in the slack chamber for sensing the offset of lead wire in the wind stream. The wire sensors are coupled to sensor and control logic for controlling the delivery and feeding of lead wire from a spool into the slack chamber.

Abstract: A closed loop integrated circuit temperature stabilizer 10 has an on-chip temperature sensor 12 for supplying a voltage indication of temperature to an op amp 22 which maintains chip temperature equilibrium by controlling a load transistor 30 which draws current through on-chip heating means 16.

Abstract: This invention provides a single integrated circuit device which replaces the non-integrated "encapsulated circuit" of the standard prior art telephone set. The circuit of this invention achieves proper D.C. regulation of the telephone line, by presenting one of several possible D.C. impedances to the telephone line when the telephone set is in the off-hook condition. The circuit of this device provides such regulation by varying the gain relationship of the telephone set for various distances from the central switching office, thereby maintaining a rather uniform signal amplitude in a plurality of telephone sets located at various distances from the central switching office. In one embodiment, this is done using a novel regulator substantially completely formed as part of a single integrated circuit chip containing a receiver amplifier, transmitting amplifier, dialing circuitry and ringing circuitry.

Abstract: An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

Abstract: A data channel for a digital tester includes a random access local memory containing a main vector sequence, a subroutine vector sequence, and a test vector list. An index register is loaded with the address of the first vector in the list of vectors that is to be inserted as a variable into a vector stream. A sequence instruction selects the index register as the source of a test vector address when a variable vector is to be inserted into the vector stream at a point in a subroutine. The sequence instruction also resets the index register to a state which determines the address of the next variable to be inserted into the test vector pattern.

Abstract: A method and system for loading test data into individual pin memories of an automatic digital test system, particularly of the in-circuit type. Test data in the form of test vectors are accessed from a test vector store simultaneously with the access of a digital test pin selection signal. The test pin selection signal accessed with the test data is then used to selectively load the test data into a pin memory identified by the pin selection signal, thereby permitting the loading of test data into any one of a group of individual pin memories. In the preferrred embodiment the test data, a test vector, is stored in a test vector store in association with a test pin selection signal. When the test vector is read from memory, the test pin selection signal is also read by the same address signal.

Abstract: A low temperature insulating glass for use in semiconductor devices comprises a mixture of germanium, silicon, oxygen and phosphorus. In the preferred embodiment, the glass comprises a mixture of about 40% to 55% silicon dioxide (SiO.sub.2), about 55% to 40% of germanium dioxide (GeO.sub.2) and from 1% to about 5% of phosphorus pentoxide (P.sub.2 O.sub.5), by mole percent.

Abstract: A method for impregnating copper into aluminum interconnect lines on a semiconductor device is disclosed. In a first embodiment, an interconnect pattern is formed on an aluminum layer by etching while the aluminum is substantially free from copper, and the copper is thereafter introduced to the formed interconnect lines. In a second embodiment, copper is introduced to the aluminum layer prior to formation of the desired interconnect pattern. The copper-rich layer is removed from the areas to be etched prior to etching. The method facilitates chlorine plasma etching of the aluminum which is inhibited by the presence of copper. The method is also useful with various wet etching processes where the formation of a copper-rich layer is found to stabilize the aluminum layer during subsequent processing .

Abstract: A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PN junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

Abstract: A current bypass for a microelectric memory, such as a static RAM, diverts word line discharge current such that the current does not flow through the memory cells of a selected word line or along an upper word line conductor. In a first embodiment, the bypass comprises a resistor R1 (R2) and a diode D10 (D20) in series and coupled between an upper word line conductor 50 and word line discharge current source V.sub.CC, and a lower word line conductor 51 and word line discharge current sink 42. In another embodiment of the invention, a transistor Q10 (Q20) is used in lieu of the diode. By bypassing current from the upper word line conductor and word line memory cells, metal migration is eliminated and narrower metal lines may be used to form the word lines. By eliminating a flow of steady state discharge current through the memory cells, memory cell current saturation is eliminated.

Abstract: A process and resulting structure are disclosed for forming vias in integrated circuit structures using metal silicide interconnections. A lower conductor is formed by sequentially depositing silicon and a refractory metal which reacts with the silicon to create a layer of metal silicide. A subsequent layer of silicon is deposited on the surface of the metal silicide. This layer of silicon is insulated from overlying layers by forming insulating material over desired regions of the layer of silicon. A second layer of metal is then deposited across the structure. In openings in the insulating material the metal reacts with the second layer of silicon to form a via of metal silicide. A final layer of silicon may be deposited to convert any remaining metal in the second layer of metal to metal silicide, and the structure annealed to lower its resistivity.

Abstract: Apparatus is provided for delaying an electrical signal present at a selected node. The apparatus includes a first multiplexer 71 which connects one of eight inputs I.sub.0 -I.sub.7 to an output terminal 75, an adjustable length delay line 72 is coupled between each pair of input terminals I.sub.0, I.sub.7, and the input signal is then supplied to the first input terminal of the multiplexer 71. The delay lines 72 are trimmed to create the desired time delay between input terminal 74 and output terminal 75.For larger adjustments of the time delay for the signal is supplied to input terminal 74 and supplied to another terminal 78 connected to the input terminal I.sub.0 of another multiplexer 61. Logic gates 62-67 are connected between each pair of terminals I.sub.0 -I.sub.6 of the second multiplexer 61. A coarser adjustment of the time delay than achievable with the delay lines 72 is made by switching of an appropriate input terminal of the second multiplexer 61 to the output terminal 69 of the multiplexer 61.

Abstract: Apparatus is provided for substituting a spare column of memory cells in a byte wide memory for a defective column of cells in such memory. The apparatus includes a spare column of memory cells, an electrically conductive line 13, a spare decoder 16 for switchably connecting the line 13 to the spare column, a first fuse FSD.sub.1 between the spare column and the line 13, a series of second fuses FS controlling a series of switches T.sub.1, T.sub.2 . . . between the line 13 and corresponding sense amplifiers 11, and a series of third fuses FD, each connected between a corresponding column and the sense amplifier associated with that column. The spare column of memory cells is connected to the appropriate sense amplifier by blowing the appropriate fuse FS and supplying the necessary address information to spare decoder 16. The defective column of memory cells may be disconnected by blowing the appropriate fuse FD.

Abstract: A CMOS buffer for the dynamic translation of input signals at TTL levels to corresponding signals at CMOS levels. A reference voltage at a level between the 0.8 volt maximum TTL "0" input level and the 2.4 volt minimum "1" input level is generated by charge distribution between capacitors. This reference level is compared with an input signal level in a dynamic comparator comprised of a CMOS cross-coupled latch to produce output signals at CMOS levels that correspond to the TTL input signals.

Abstract: The disclosure relates to techniques for etching layered materials to produce features with beveled edges, for example, wells in silicon oxide layers employed in integrated circuit fabrication. An anisotropic etch may be employed to form wells with vertical walls in the silicon oxide layer, and an isotropic etch may be employed to bevel peripheral corners of the walls. In preferred embodiments, a double mask of a photoresist layer on an underlying thin film may be used to define the limits of the anisotropic and isotropic etches, respectively.

Abstract: A circuit for use in controlling a memory cell coupled to a word line W and to first and second bit lines B1 and B2 includes an enabling flip-flop 20 having set terminal S connected to a source of enabling signals and a reset terminal R connected to an OR gate 22; a word line addressing circuit 25 connected to the output of the enabling flip-flop 20 and to the word line W, and having a terminal ADDR for receiving address information; first and second read/write circuits 29 and 30 connected to corresponding first and second bit lines B1 and B2, respectively, each of the read/write circuits 29 and 30 including a control node WRC and an output node SADO; a logic gate 22 having an output coupled to the reset terminal and having input nodes SADO 0 and SADO 1 connected to the corresponding output nodes of the read/write circuits 29 and 30, and an output flip-flop 33 connected the output nodes SADO 0 and SADO 1 of the read/write circuits 29 and 30.

Abstract: A method, timing control circuit, and power supply are described for initiating arc discharge between the cover gas delivery shroud and lead wire held in the bonding tool of a lead wire bonding machine for melting and forming a ball at the end of the lead wire. An arc discharge timing control pulse controls duration of the arc discharge within an empirically determined time window between the shortest and longest durations of arc discharge which result in optimal ball formation of a substantially spherical ball at the end of the lead wire without necking of the lead wire above the formed ball. The timing control circuit also provides an initial cover gas movement delay before ball formation for displacing oxygen from the shield and the end of the lead wire, and a subsequent cooling delay for solidifying and cooling the formed ball in the cover gas stream prior to ball bonding.

Abstract: In a microprocessor having independent address and data paths and other pipeline architecture features, a control unit utilizes a PLA which stores microcoded instruction sequences. These sequences permit an operator at a console to read data from and write data to all the internal registers, any external memory location or the program counter. In addition, the PLA contains microcode which enables programs in external memory to be loaded from any location in memory and run by command from the console as well as to enable the operator to halt user program execution, read the pertinent internal registers, and then continue program execution such that single step execution for debug purposes is possible.

Abstract: An improved tristate enable circuit is described for activating a tristate enable gate to maintain the high impedance third state of a common bus tristate output device during "power down" and "power up" transitions of the common power supply V.sub.cc. The enable gate circuit element tends to turn off at a voltage level V.sub.cc2 generally greater than the voltage level V.sub.cc3 at which the tristate output device circuit elements turn off. As a result the high impedance state may be lost during "power down". A threshold activation circuit is coupled to the enable gate for activating the enable gate when the threshold activation circuit senses a higher common power supply voltage level V.sub.cc1. The threshold activation circuit operatively activates the enable gate over a voltage range from V.sub.cc1 to a lesser common power supply voltage level V.sub.cc4. Component values are selected for relating the voltage levels so that V.sub.cc1 >V.sub.cc2 and V.sub.cc3 >V.sub.cc4.

Abstract: A structure and method are provided wherein a single output buffer stage (50) is provided which can be programmed to function either as an open drain output buffer or a CMOS Push-Pull output buffer. The output buffer stage constructed in accordance with this invention is programmed in one of several manners. In one embodiment of this invention, the fabrication steps utilized to program the output buffer are the enhancement and depletion dopings, whereby certain devices of the output buffer are programmed to either remain always turned off or always turned on, thus programming the output buffer to serve either as an open drain output buffer or as a CMOS push-pull output buffer.