Abstract: The present invention discloses a transmitted/received data decoding method and apparatus, which achieve effects of decoding performance improvement and synchronous detection. The decoding method includes setting a coded edge pattern, and filtering a received data by using the set coded edge pattern as a window; respectively computing absolute values of filtered values filtered by using the coded edge pattern windows; detecting a maximum absolute value from the computed absolute values; determining a sign (+/?) for the detected maximum absolute value; outputting an intermediate bit value of the corresponding original data as a resultant decoded value according to the determined sign and a window type (i.e. coded edge patter) with the selected maximum absolute value.

Abstract: An estimating method for maximum channel delay and cyclic prefix (CP) averaging method in orthogonal frequency division multiplexing (OFDM) receiver are described. Specifically, the estimating method performs the estimation of the maximum channel delay by adding the CP and the main OFDM signal for increasing the signal-to-noise ratio (SNR) and for reducing the inter-carrier interference (ICI). The CP averaging method is used to acquire a portion of the CP by using the maximum channel delay so as to increase the performance of the OFDM receiver.

Abstract: A multi-channel receiver capable of minimizing an interference effect occurring among mounted receivers and a method of reducing interference of the multi-channel receiver capable of minimizing the interference effect occurring among the mounted receivers are provided. The multi-channel receiver includes an antenna, a first receiver, and a second receiver. The antenna receives an RF signal in a predetermined frequency band. The first receiver down-converts the RF signal received through the antenna into a first IF signal. The second receiver down-converts the RF signal received through the antenna into a second IF signal. Here, the first and second receivers down-convert the RF signal by exclusively using a local oscillation frequency signal generated by using a low side LO injection method or a local oscillation frequency signal generated by using a high side LO injection method.

Abstract: A method and an apparatus for audio noise reduction of frequency modulation (FM) receiver are described. After receiving FM signal having pilot tone, pilot carrier sync detector performs pilot carrier synchronization detection of FM signal, FM demodulator demodulates synchronized FM signal, multiplex decoder decodes audio signal of demodulated FM signal for outputting the decoded audio signal, and noise reduction controls multiplex decoder for controlling noise attenuation associated with the decoded audio signal according to RSSI, the method comprising the steps: (a) performing phase error detection for detecting phase error of phase-locked loop (PLL) of pilot carrier sync detector; (b) determining whether noise exists by comparing the phase error with threshold value to determine whether noise exists in the phase error; and (c) performing noise reduction step by outputting noise reduction control signal to noise reduction based on determination in step (b) for reducing noise in the noise existence interval.

Abstract: The present invention discloses a transmitted/received data decoding method and apparatus, which achieve effects of decoding performance improvement and synchronous detection. The decoding method includes setting a coded edge pattern, and filtering a received data by using the set coded edge pattern as a window; respectively computing absolute values of filtered values filtered by using the coded edge pattern windows; detecting a maximum absolute value from the computed absolute values; determining a sign (+/?) for the detected maximum absolute value; outputting an intermediate bit value of the corresponding original data as a resultant decoded value according to the determined sign and a window type (i.e. coded edge patter) with the selected maximum absolute value.

Abstract: An apparatus and a method for frequency calibration in a frequency synthesizer are disclosed. The present invention includes an up/down processor. The up/down processor is utilized for outputting one of a GND voltage and a VDD voltage to a voltage-controlled oscillator via a loop filter in an open loop status, or outputting one of a step-up voltage and a step-down voltage in accordance with a phase difference to the voltage-controlled oscillator via the loop filter in a close loop status. When the up/down processor outputs one of the GND voltage and the VDD voltage in the open loop status, a memory bank selector compares frequencies for selecting a value of a memory bank and then adds an offset to the value of the memory bank so as to determine a final value of a VCO memory bank in the phase locked loop.

Abstract: A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment.

Abstract: A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment.

Abstract: Provided is a modulation-index adjustable amplitude shift keying (ASK) transmitter including: a bias current supply unit supplying one or more bias currents in response to a digital signal that is to be transmitted and one or more bias current control signals; and a modulation signal generator generating a modulation signal corresponding to the digital signal by modulating a carrier signal in response to the one or more bias currents.

Abstract: The present invention relates to a direct current (DC) offset suppression circuit to suppress DC offsets occurring when a communication circuit where a complex filter is adopted performs self-mixing. The DC offset is suppressed by a DC feedback circuit adopted by a filter which is substituted for a complex filter in the communication circuit. But, the DC offset cannot be suppressed when a complex filter is used in the communication circuit. It is because phase changes of the complex filter cause output signal fed back to the input of the complex filter to generate phase differences. The present invention includes a phase compensation unit and a DC feedback unit. The phase compensation unit compensates a change in frequency between input and output of the complex filter for phase compensation. The DC feedback unit inverses and feeds back the compensated phase to an input of the complex filter.

Abstract: The present invention discloses a mixer circuit for mixing two input signals by source-coupled MOS transistors and outputting a mixed result. A duty cycle controlling MOS transistor is connected to a source of each source-coupled MOS transistor in series. A duty cycle controlling pulse is applied to a gate of the duty cycle controlling MOS transistor. The duty cycle controlling pulse has a phase shift of ?90 degrees with respect to a controlling pulse applied to the gate of the source-coupled MOS transistor connected with the duty cycle controlling MOS transistor in series. An AND-combination of the duty cycles of the two controlling pulses applied to the gates of the two MOS transistors connected in series can be controlled at 25%. Comparing to the conventional mixer circuit having a switch control duty cycle of 50%, the present invention achieves the effects of increasing the gain and reducing the noise figure.

Abstract: A peak detector capable of rapidly detecting a peak value of a signal is provided. The peak detector includes first and second operational amplifiers and an auxiliary current source to detect two rail to rail signals. The first operational amplifier outputs a detection signal by buffering a first rail to rail input signal. The second operational amplifier outputs a control signal in response to a second rail to rail input signal and the detection signal. The auxiliary current source includes a terminal connected to an output terminal of the first operational amplifier and the other terminal connected to the first or second source voltage. The auxiliary current source operates in response to the control signal. The auxiliary current source supplies a current from the first source voltage to the output terminal in response to the control signal or supplies a path for discharging a current from the output terminal to the second source voltage.

Abstract: Provided is a receiver capable of automatically controlling a gain of the receiver and receiving three or more band signals. A gain controlled receiver includes a low noise amplifier, a first variable gain control amplifier, a frequency mixer, a filter, a second variable gain control amplifier, and a gain control block. The gain controlled receiver automatically controls gains of the low noise amplifier, the first variable gain control amplifier, the frequency mixer, the filter, the second variable gain control amplifier by detecting strength of the signals processed in the receiver. Therefore, without an additional manual tuning operation, the gain of the receiver can be automatically maintained in an optimal state. A multi-band processing receiver includes a first receiving unit, a second receiving unit, and a switch. The multi-band processing receiver can process three or more RF signals in multi-band by using a single receiver.

Abstract: A variable gain amplifier (VGA) with a linear-in-dB gain characteristic is provided. The VGA includes: a control signal converter which converts an input gain control signal VC, which is input so that the VGA obtains a linear-in-dB gain characteristic to the maximum gain, into an output gain control signal Vx=VTln((1/m)exp(?VC/VT)?1) (m is a constant, VT=kT/q); and a variable gain amplifier which receives and converts the output gain control signal VX output from the control signal converter so that the gain has a linear-in-dB characteristic. A shape of a gain curve is externally controlled.

Abstract: Provided are an image signal rejection method capable of avoiding demodulation of an image signal along with a real signal in a radio frequency (RF) signal and a low IF receiver of rejecting an image signal by using the method. The low IF receiver of rejecting an image signal includes a low noise amplifier, a quadrature I/Q mixer, a signal complex filter, and a phase and gain control block. The low noise amplifier amplifies a radio frequency (RF) signal. The quadrature I/Q mixer generates an I signal and a Q signal by down-converting the amplified RF signal into an IF signal. The phase and gain control block generates an I? signal and a Q? signal which are obtained by changing phases and amplitudes of the I signal and the Q signal by using a real signal. The signal complex filter minimizing the image signal in the IF signal and passing the real signal by performing filtering on the I? signal and the Q? signal.

Abstract: An estimating method for maximum channel delay and cyclic prefix (CP) averaging method in orthogonal frequency division multiplexing (OFDM) receiver are described. Specifically, the estimating method performs the estimation of the maximum channel delay by adding the CP and the main OFDM signal for increasing the signal-to-noise ratio (SNR) and for reducing the inter-carrier interference (ICI). The CP averaging method is used to acquire a portion of the CP by using the maximum channel delay so as to increase the performance of the OFDM receiver.

Abstract: Provided is a poly-phase filter capable of removing an image frequency of a terrestrial digital multimedia broadcasting (T-DMB) receiver in a low intermediate frequency (IF) structure applied to a mobile communication terminal and a receiver having the poly-phase filter. The poly-phase filter includes: a calibration control block for generating first and second filter characteristic control signals which determine electrical characteristics of the filter in response to a control signal including instructions for changing the characteristics of the poly-phase filter and holding the changed values; and a poly-phase filter block for performing filtering on a plurality of input signals having different phases from each other in response to the first and second filter characteristic control signals. Accordingly, the poly-phase filter has advantages of having constant electrical characteristics regardless of changes in a manufacturing process and temperature and a high-performance image rejection function.

Abstract: A frequency synthesizer capable of using a voltage controlled oscillator (VCO) with a low value of gain Kvco, having a short automatic frequency calibration time and automatically coping with environments and a frequency calibration method are provided. The frequency synthesizer includes a reference divider, a phase detector, a main divider, a charge pump, a loop filter, a first switch, a second switch, a VCO, and an automatic frequency calibration block. The frequency calibration method includes an initialization step, an N-target algorithm step, an auxiliary search algorithm step, and a post search algorithm step.

Abstract: The mixer includes mixers constructed with variable gain amplifiers having two transistor pairs Qp+/Qp? and Qn+/Qn? to have a predetermined gain by using LO+ and LO? signals; and LO bias circuits connected to have bias voltages different from each other with respect to the LO+ and LO? signals of the mixers and share an input signal.

Abstract: A low noise reference voltage circuit without using an amplifier inside is capable of transforming a current IPTAT in positive proportion to absolute temperature into a voltage VPTAT in positive proportion to absolute temperature, and outputting it to a ring oscillator. The low noise reference voltage circuit improves a degradation of noise performance compared with a conventional band-gap reference voltage circuit and is in characteristic of low noise and higher PSRR.