Abstract: Aspects of the present disclosure include an optoelectronic assembly with a housing that defines a cavity and includes a first component and a glass component disposed on an opposite side of the cavity from the first component. The glass component may include a first surface and a second surface and a lens located on the first surface. An optical transmitter and/or an optical receiver may be mechanically coupled to the first component within the cavity and oriented to emit optical signals through the glass component and the lens. Conductive traces may be located on the second surface of the glass component and electrically coupled to the optical transmitter and/or the optical receiver. An electronic component may be coupled to at least one of the conductive traces.

Abstract: An example embodiment includes optical receiver that includes a polarization beam splitter (PBS), a polarization controller, and a forward error correction (FEC). The PBS is configured to split a received optical signal having an unknown polarization state into two orthogonal polarizations (x?-polarization and y?-polarization). The polarization controller includes no more than two couplers and no more than two phase shifters per wavelength channel of the x?-polarization and the y?-polarization. The polarization controller is configured to demultiplex the x?-polarization and the y?-polarization into a first demultiplexed signal having an first polarization on which a data signal is modulated and a second demultiplexed signal having a second, orthogonal polarization on which a pilot carrier oscillator signal is encoded. The FEC decoder module is configured to correct a burst of errors resulting from resetting one of the phase shifters based on error correction code (ECC) data encoded in the data signal.

Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.

Abstract: In an example, a coupled system includes a first waveguide, at least one second waveguide, and an interposer. The first waveguide has a first refractive index n1 and a tapered end. The at least one second waveguide each has a second refractive index n2. The interposer includes a third waveguide having a third refractive index n3 and a coupler portion, where n1>n2>n3. The tapered end of the first waveguide is adiabatically coupled to a coupler portion of one of the at least one second waveguide. A tapered end of one of the at least one second waveguide is adiabatically coupled to the coupler portion of the third waveguide of the interposer. The coupled system is configured to adiabatically couple light between the first waveguide and the at least one second waveguide and between the at least one second waveguide and the third waveguide.

Abstract: In an embodiment, a delay line interferometer (DLI) multiplexer (MUX) includes a first stage and a second stage. The first stage includes a first DLI and a second DLI. The first DLI includes a first left input, a first right input, and a first output and has a free spectral range (FSR) that is about four times a nominal channel spacing. The second DLI includes a second left input, a second right input, and a second output and has an FSR that is about four times the nominal channel spacing. The second stage is coupled to the first stage and includes a third DLI. The third DLI includes a third left input optically coupled to the first output, a third right input optically coupled to the second output, and a third output. An FSR of the third DLI is about two times the nominal channel spacing.

Abstract: A linecard includes at least one pluggable device, a linecard processor, and a centralized host processor. The linecard also includes an interface that supports a pluggable device. A pluggable device is electrically coupled to the interface and is controlled by the centralized host processor. A flash memory stores data for the pluggable device. The pluggable device can include at least one of an optical amplifier and a ROADM pluggable device.

Abstract: In some examples, a transmit assembly is described that may include a first optical transmitter, a second optical transmitter, and a polarizing beam combiner. The first optical transmitter may be configured to emit a first optical data signal centered at a first frequency. The second optical transmitter may be configured to emit a second optical data signal centered at a second frequency offset from the first frequency by a nominal offset n. The polarizing beam combiner may be configured to generate a dual carrier optical data signal by polarization interleaving the first optical data signal with the second optical data signal. An output of the polarizing beam combiner may be configured to be communicatively coupled via an optical transmission medium to a polarization-insensitive receive assembly.

Abstract: A circuit may include an input terminal configured to receive an input signal with a first voltage swing and an output terminal. The circuit may also include a first transistor, a second transistor, a third transistor, and a control circuit. The control circuit may be coupled to the input terminal, a gate terminal of the first transistor, and a gate terminal of the second transistor. The control circuit may be configured to adjust voltages provided to the gate terminals based on the input signal such that the first transistor conducts in response to the input signal being at a first logical level and the second transistor conducts in response to the input signal being at a second logical level to generate an output signal output on the output terminal. The second voltage swing of the output signal may be different from the first voltage swing of the input signal.

Abstract: A laser module can include: a laser chip having a plurality of laser diodes; a focusing lens optically coupled to each of the plurality of distinct laser diodes; and a photonic integrated circuit (PIC) having a plurality of optical inlet ports optically coupled to the plurality of laser diodes through the focusing lens. The laser module can include an optical isolator optically coupled to the focusing lens and PIC and positioned between the focusing lens and PIC. The laser chip can include a fine pitch laser array. The laser module can include a plurality of optical fibers optically coupled to an optical outlet port of the PIC. The laser module can include a hermetic package containing the laser chip and having a single focusing lens positioned for the plurality of laser diodes to emit laser beams there through.

Abstract: An example embodiment includes a communication module. The communication module includes a shell, a printed circuit board assembly (“PCBA”) at least partially positioned within the shell, an optical transmitter electrically coupled to the PCBA, an optical receiver electrically coupled to the PCBA, and a biasing assembly. The biasing assembly includes a latch cover configured to be attached to the shell, a slider, and a spring. The slider is configured to operate a latching mechanism that releasably connects the module to a host device through a mechanical connection. The slider includes a main body including a first end, an arm extending from the first end, and a stopper feature extending from the arm. The spring is positioned between the latch cover and the stopper feature to bias the latching mechanism.

Abstract: A connector includes pins having a pinout including a functional designation cadence. The functional designation cadence includes a first ground pin, a first signal pin, a no-connect pin, a second signal pin, and a second ground pin, where the first signal pin is positioned between the first ground pin and the no-connect pin, the no-connect pin is positioned between the first and second signal pins, and the second signal pin is positioned between the no-connect pin and the second ground pin. Alternately, the functional designation cadence includes a first ground pin, a first signal pin, a third ground pin, a second signal pin, and a second ground pin, where the first signal pin is positioned between the first and third ground pins, the third ground pin is positioned between the first and second signal pins, and the second signal pin is positioned between the third and second ground pins.

Abstract: Latch mechanisms for modules are disclosed. A module includes a housing and a release slide. The housing includes a first rib located on a first side of the housing and a second rib located on a second side of the housing. The release slide is slidingly positioned on the housing. The release slide includes a release slide base, a first release slide arm extending from the release slide base, and a second release slide arm extending from the release slide base. A first flange extending from the first release slide arm is positioned at least partially over the first rib. A second flange extending from the second release slide arm is positioned at least partially over the second rib.

Abstract: Multi-laser transmitter optical subassembly (TOSA). In one example embodiment, a method of fabricating a multi-laser TOSA includes various acts. First, first and second optical signals are transmitted from first and second lasers, respectively. Next, the angle of a first collimating lens is actively adjusted to cause the second optical signal to be aligned with the first optical signal as the first optical signal passes through a first filter and as the second optical signal is reflected by the first filter such that the first and second optical signals are aligned and combined.

Abstract: Transmissive diffraction grating(s), reflector(s), and multiple optical sources/receivers are arranged such that each one of multiple optical signals at corresponding different wavelengths co-propagating along a multiplexed beam path would: (i) be transmissively, dispersively diffracted at a multiplexed transmission region of a grating; (ii) propagate between the multiplexed transmission region and multiple demultiplexed transmission regions of a grating undergoing reflection(s) from the reflector(s); (iii) be transmissively, dispersively diffracted at the demultiplexed transmission regions; and (iv) propagate between the demultiplexed transmission regions and the sources/receivers along multiple demultiplexed beam paths.

Abstract: One example embodiment includes an optical subassembly (OSA). The OSA includes a flex circuit, an optical port, and an active optical component subassembly. The flex circuit is constructed of at least one electrically-conductive layer and at least one electrical insulator layer. The optical port defines a barrel cavity and is mechanically coupled to the flex circuit at a flex connection. The active optical component subassembly is positioned within the barrel cavity and electrically coupled to the flex circuit.

Abstract: A DPSK/DQPSK receiver includes an optical splitter that separates the received DPSK/DQPSK optical signal according to an optical power splitting ratio into a plurality of received optical signals. A plurality of optical filters passes a plurality of filtered received optical signals. A plurality of optical detectors generates a plurality of electrical detection signals, each with a power that is related to a power of a respective filtered optical signal. A plurality of amplifiers generates a plurality of amplified electrical signals. At least one electrical signal combiner combines the plurality of amplified electrical detection signals generated by the plurality of optical amplifiers into a combined reception signal.

Abstract: In an embodiment, a polarization-dependent loss (PDL) compensator includes a substrate, an anti-reflective coating, and a partial reflective coating. The substrate has an input surface and an output surface opposite the input surface. The anti-reflective coating is formed on the output surface. The partial reflective coating is formed on the input surface. The PDL compensator may include PDL that depends on an incident angle of an optical signal with respect to the partial reflective coating.

Abstract: A printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate forms a first layer of the printed circuit board. The AIN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.

Abstract: An avalanche photodiode can include: an avalanche region having one or more layers prepared from GaAs; an N? absorption layer extending across the avalanche region; an N-type layer above at least a center portion of the N? absorption layer; and optionally a lower conductivity layer laterally from the N-type layer to a surface of the avalanche region and above a perimeter portion of the N? absorption layer, the lower conductivity layer having lower conductivity compared to the N-type layer. The avalanche photodiode can include a window layer above the N-type layer and lower conductivity layer, and an anode contact above the window layer. The avalanche photodiode can include an N+ barrier layer below the N? absorption layer, an N+ conduction layer below the N+ barrier layer, a substrate below the N+ conduction layer, and a cathode contact coupled with the N+ conduction layer.

Abstract: A VCSEL can include a graphene intra-cavity absorber having at least one graphene region and at least one dielectric region adjacent to the graphene region. The VCSEL can also include a graphene electrode electronically coupled with at least one graphene region. The VCSEL can also include a contact region adjacent with at least one dielectric region. The VCSEL can also include a contact electrode electronically coupled with the contact region. The VCSEL can also include a base electrode electronically coupled with a base of a semiconductor region of the VCSEL. The graphene intra-cavity absorber can include at least two graphene regions sandwiching at least one dielectric region therebetween.