Patents Assigned to Flexenable Limited
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Patent number: 10325985Abstract: A technique comprising: providing a stack of layers defining at least (a) source and drain electrodes, (b) gate electrode, and (c) semiconductor channel of at least one transistor; depositing one or more organic insulating layers over the stack; removing at least part of the stack in one or more selected regions by an ablation technique; depositing conductor material over the stack in at least the one or more ablated regions and one or more border regions immediately surrounding a respective ablated region; and depositing inorganic insulating material over the stack at least in the ablated regions and the border regions to cover the ablated regions and make direct contact with said conductor material in said one or more border regions all around the respective ablated region.Type: GrantFiled: July 21, 2015Date of Patent: June 18, 2019Assignee: FLEXENABLE LIMITEDInventors: Jan Jongman, Anja Wellner, Jens Dienelt, Karsten Neumann, Stephan Riedel
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Publication number: 20190148417Abstract: A technique comprising: providing an assembly temporarily adhered on opposite sides to respective carriers by respective adhesive elements, the assembly including at least one plastic support sheet; heating the assembly while mechanically compressing the assembly between the carriers, wherein the strength of adhesion of one of said adhesive elements to the respective carrier and/or to the assembly is partially reduced during said heating of the assembly under mechanical compression; and wherein the strength of adhesion of the said adhesive element to the carrier and/or to the assembly is further reducible by further heating the said adhesive element after partially or completely relaxing the pressure at which the assembly is mechanically compressed between the two carriers.Type: ApplicationFiled: May 11, 2017Publication date: May 16, 2019Applicant: FLEXENABLE LIMITEDInventor: Barry WILD
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Publication number: 20190088790Abstract: A device, comprising: an unplanarised plastic substrate; an electrically and/or optically functional layer formed on the unplanarised substrate; a planarisation layer formed over the functional layer; at least a first conductor layer and a semiconductor layer formed over the planarization layer, wherein the first conductor layer defines at least source and drain electrode circuitry for one or more transistor devices, and the semiconductor layer defines semiconductor channels for said one or more transistor devices.Type: ApplicationFiled: September 18, 2018Publication date: March 21, 2019Applicant: Flexenable LimitedInventors: Matthew James Harding, Mike Banach
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Publication number: 20190013472Abstract: A technique, comprising: forming a stack comprising a semiconductor layer for providing the semiconductor channels of one or more transistors, and an insulator layer; and patterning the stack so as to form in a single process both: (i) one or more interconnection holes for connecting a conductor level on one side of the stack to a conductor level on the opposite side of the stack; and (ii) one or more leakage reduction trenches for reducing leakage paths via the semiconductor between conductor elements on one side of the stack.Type: ApplicationFiled: February 9, 2017Publication date: January 10, 2019Applicant: FLEXENABLE LIMITEDInventor: Elizabeth SPEECHLEY
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Patent number: 10130319Abstract: A device, comprising: a display component; and a drive component comprising a stack of layers defining an array of display pixel conductors each connected within the stack of layers to a drive conductor by a respective radiation-sensitive channel, wherein a change in the intensity of radiation to which a radiation-sensitive channel is exposed causes a change in the electric potential at the respective display pixel conductor relative to a drive voltage applied to the drive conductor and the change in the electric potential at the respective display pixel conductor causes a change in the display of the respective pixel area of the display component.Type: GrantFiled: July 2, 2014Date of Patent: November 20, 2018Assignee: FLEXENABLE LIMITEDInventor: Matthew James Harding
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Publication number: 20180313778Abstract: A technique for producing a device for sensing a target species, comprising: providing first end second components, each comprising a support film, wherein at least one of said first and second components comprises at least one working electrode supported on the respective support film, at least one of said first and second components comprises at least one counter electrode supported on the respective support film, at least one of said first and second components defines a containing barrier supported on the respective support film, and at least one of said first and second components comprises an array of spacer structures supported on the respective support film; depositing a volume of liquid electrolyte on said first component; laminating said second component to said first component so as to spread said volume of liquid electrolyte out in a space created by said array of spacer structures within a liquid electrolyte area bounded by said containing barrier; wherein said liquid electrolyte functions to traType: ApplicationFiled: October 6, 2016Publication date: November 1, 2018Applicant: FLEXENABLE LIMITEDInventors: Micheal James BANACH, Guillaume FICHET
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Patent number: 10109682Abstract: A method of producing a transistor array, comprising an array of addressing conductors each providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; wherein the method comprises: forming a conductor layer on a support; and displacing a plurality of portions of said conductor layer relative to other portions of said conductor layer to create from said conductor layer at least (i) said array of addressing conductors and an array of drain conductors at said first level, (ii) conductor element islands in transistor channel regions at a second level, and (iii) one or more further conductor elements at a third level.Type: GrantFiled: May 20, 2015Date of Patent: October 23, 2018Assignee: FLEXENABLE LIMITEDInventor: Matthew James Harding
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Publication number: 20180297345Abstract: A method for producing electronic devices or components therefor comprising providing first and second components for laminating together the first and second components to define active areas. Then, applying adhesive to the first and/or second components, and successively laminating increasingly distal portions of said second component to the first component in a lamination direction. At least a part of the adhesive applied to the first and/or second components in an area downstream of active areas in the lamination direction defines an array of pairs of line sections of adhesive, each pair of line sections converging to a respective meeting point in a direction opposite to said lamination direction. The array of pairs of line sections extends continuously across substantially the whole lateral width of said one or more active areas, without any spaces or lateral line sections between each pair of lines sections in the array.Type: ApplicationFiled: October 6, 2016Publication date: October 18, 2018Applicant: FLEXENABLE LIMITEDInventors: Barry WILD, William Henry REEVES
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Publication number: 20180290443Abstract: A technique for forming a plurality of liquid cells for a plurality of electronic devices, comprising: providing first and second components for laminating together to contain a liquid material; wherein at least one of the first and second components comprises spacing structures for maintaining a separation distance between the first and second components in at least two active area regions for two electronic devices; providing liquid material on at least one of the first and second components, wherein a sufficient amount of said liquid material for the whole of each active area region is provided in a respective starting area upstream of the respective active area region in the lamination direction; and successively laminating increasingly distal portions of the second component to the first component in a lamination direction, according to a technique by which said liquid material is spread out from said starting areas at least over said at least two active area regions; wherein said at least two active areType: ApplicationFiled: October 6, 2016Publication date: October 11, 2018Applicant: FLEXENABLE LIMITEDInventors: Barry WILD, William Henry REEVES
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Patent number: 10096788Abstract: A transistor device comprising: source and drain conductors connected by a semiconductor channel; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein the gate conductor comprises at least one portion overlapping at least part of at least one of said source and drain conductors; and further comprising a patterned insulator interposed between at least part of said at least one of the source and drain conductors and said at least one overlapping portion of said gate conductor so as to reduce capacitive coupling between the said at least one of the source and drain conductors and the gate conductor by more than any reduction in capacitive coupling between the semiconductor channel and the gate conductor.Type: GrantFiled: December 9, 2014Date of Patent: October 9, 2018Assignee: FLEXENABLE LIMITEDInventor: Jan Jongman
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Publication number: 20180190918Abstract: An electronic or optoelectronic device including a semiconductor layer, wherein the semiconductor layer comprises at least a semiconductive organic material, water species, and at least one additive in an amount of at least 0.1% by weight relative to the semiconductive organic material, which additive at least partly negates a charge carrier trapping effect caused by the water species on the semiconductive organic material.Type: ApplicationFiled: June 29, 2016Publication date: July 5, 2018Applicants: FLEXENABLE LIMITED, CAMBRIDGE ENTERPRISE LIMITEDInventors: Henning SIRRINGHAUS, Mark NIKOLKA, Iyad NASRALLAH, Jan JONGMAN
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Patent number: 9985207Abstract: A method of producing an electronic device including the steps of: (i) providing a body including a first, conductive element separated from a first surface of said body by a portion of said body; (ii) removing a selected portion of said body to define a recess in said body extending from said first surface and via which a portion of said first element is exposed; and (iii) putting into said recess a liquid medium carrying a first material; wherein said first material is preferentially deposited on the exposed inner surface of said body defining said recess, and wherein the deposited first material is used to provide a connection between said first element and a second conductive element located within said body or later deposited over said first surface of said body.Type: GrantFiled: December 6, 2005Date of Patent: May 29, 2018Assignee: FLEXENABLE LIMITEDInventors: Carl Hayton, Henning Sirringhaus, Timothy Von Werne, Shane Norval
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Patent number: 9984634Abstract: A method of displaying color data on an electronic paper display is displayed. The method comprises providing an electronic paper display having display pixels at a display pixel pitch and providing a color filter for said display. Said color filter comprises groups of colored filter elements, each said colored filter element having one of a plurality of different colors, wherein each group of colored filter elements defines a pattern of said colored filter elements. In said pattern a colored filter element overlies an integral number, n, of said display pixels, where n is two or more. The method also comprises providing color image data defining a plurality of color image planes, one for each of said different colors. Data in a said color image plane comprises image pixel data defining values for image pixels corresponding to said display pixels.Type: GrantFiled: October 29, 2014Date of Patent: May 29, 2018Assignee: Flexenable LimitedInventor: Will Reeves
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Patent number: 9947723Abstract: A multiple layer pixel architecture for an active matrix display is provided having a common bus line on a metal level separate from that on which the gate electrodes of the thin-film transistors (TFTs) are formed. A multilayer electronic structure includes a TFT for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure includes a substrate bearing at least four conducting layers separated by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.Type: GrantFiled: March 29, 2016Date of Patent: April 17, 2018Assignee: FlexEnable LimitedInventors: Kieran Reynolds, Catherine Ramsdale, Kevin Jacobs, William Reeves
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Patent number: 9911854Abstract: A transistor device comprising: source and drain conductors connected by a semiconductor channel provided by a layer of semiconductor material formed over the source and drain conductors; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein at least one of the source and drain conductors comprises a multilayer structure in at least one region thereof, the multilayer structure comprising a lower layer and an upper layer, the material of the lower layer being better than the material of the upper layer at injecting charge into the semiconductor material; and the material of the upper layer exhibiting better electrical conductivity than the material of the lower layer.Type: GrantFiled: December 9, 2014Date of Patent: March 6, 2018Assignee: FLEXENABLE LIMITEDInventors: Jon Jongman, Brian Asplin
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Patent number: 9876034Abstract: A device comprising an array of transistors, wherein the device comprises: a first conductor layer at a first level defining a plurality of first conductors providing either source or gate electrodes for said array of transistors; a second conductor layer at a second level defining a plurality of second conductors providing the other of source or gate electrodes for said array of transistors; wherein said second conductor layer further defines routing conductors at one or more locations between said second conductors, each routing conductor connected by one or more interlayer conductive connections to a respective first conductor.Type: GrantFiled: October 7, 2014Date of Patent: January 23, 2018Assignee: FLEXENABLE LIMITEDInventor: Stephan Riedel
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Patent number: 9846346Abstract: A technique, comprising: providing a pixelated display unit comprising an array of pixels, wherein the optical output for each pixel is independently controllable; applying a first color filter overlay to a viewing surface of said pixelated display unit, said first color filter overlay defining a first color pattern including one or more areas of a single color continuously extending over a plurality of pixels; operating said pixelated display unit to produce regions of differing brightnesses within said first color pattern; peeling said first color filter overlay from said viewing surface of said display unit; applying a second color filter overlay to said viewing surface of said display unit, said second color filter overlay defining a second color pattern including one or more areas of a single color continuously extending over a plurality of pixels; and operating said pixelated display unit to produce regions of differing brightnesses within said second color pattern.Type: GrantFiled: July 21, 2014Date of Patent: December 19, 2017Assignee: FLEXENABLE LIMITEDInventors: Guillaume Fichet, William Reeves
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Patent number: 9837450Abstract: A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.Type: GrantFiled: October 7, 2014Date of Patent: December 5, 2017Assignee: FLEXENABLE LIMITEDInventors: Stephan Riedel, David Gammie, Boon Hean Pui
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Patent number: 9807876Abstract: A flexible electronic reading device, the device comprising a display part and a handle, wherein said display part comprises: a display backplane on a flexible substrate; and a display mounted over said display backplane; wherein said handle is located at one edge of said display backplane and contains display interface electronics for said display; and wherein said display part of said electronic reading device comprises a unitary, continuous structure lacking a separate housing.Type: GrantFiled: May 22, 2013Date of Patent: October 31, 2017Assignee: FLEXENABLE LIMITEDInventor: Mark Catchpole
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Patent number: 9805668Abstract: We describe a method of reducing artefacts in an image displayed by an active matrix electro-optic display and display driver, the electro-optic display driver comprising a plurality of active matrix pixel drivers each driving a respective pixel of the electro-optic display, each active matrix pixel driver having an associated storage capacitor coupled to a common backplane connection of the display driver, pixels of the electro-optic display having a common pixel electrode, the method comprising: driving the electro-optic display with a null frame during a power-down procedure of the display.Type: GrantFiled: July 8, 2013Date of Patent: October 31, 2017Assignee: FLEXENABLE LIMITEDInventors: Tiziano Agostinelli, Jeremy Hills, David Gammie, Stephan Riedel, Boon Hean Pui