Abstract: A pixel driver circuit having only three conductive layers is described. The pixel driver circuit comprises a vertical driver transistor (26) spanning said three conductive layers, wherein a first of said conductive layers (22) on a first side of a middle conductive layer (32) provides a first source-drain connection (52) of said driver transistor, wherein a third of said conductive layers (34) on the opposite side of said middle conductive layer to said first conductive layer provides a gate connection (54) for said vertical driver transistor, and wherein said middle conductive layer provides a second source-drain connection (50) for said vertical driver transistor. The circuit also comprises a lateral switching transistor (30) with source-drain connections (44,46) in one of said three conductive layers.

Abstract: A technique of operating a device comprising a patterned conductor layer defining source electrode circuitry and drain electrode circuitry for a plurality of transistors; a semiconductor layer providing a respective semiconductor channel for each transistor between source electrode circuitry and drain electrode circuitry; and gate electrode circuitry overlapping the semiconductor channels of the plurality of transistor devices for switching the semiconductor channels between two or more levels of conductance; wherein the technique comprises using one or more further conductors independent of said gate electrode circuitry to capacitatively induce a reduction in conductivity of said one or more areas of said semiconductor layer outside of said semiconductor channels.

Abstract: There is provided a method of patterning a stack of layers defining one or more electronic device elements, comprising: creating a first thickness profile in an uppermost portion of the stack of layers by laser ablation; and etching the stack of layers to translate the first thickness profile into a second thickness profile at a lower level; wherein the etching reduces the thickness of said uppermost portion of the stack and one or more lower layers of the stack under said uppermost portion.

Abstract: A transistor device comprising: source and drain conductors connected by a semiconductor channel provided by a layer of semiconductor material formed over the source and drain conductors; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein at least one of the source and drain conductors comprises a multilayer structure in at least one region thereof, the multilayer structure comprising a lower layer and an upper layer, the material of the lower layer being better than the material of the upper layer at injecting charge into the semiconductor material; and the material of the upper layer exhibiting better electrical conductivity than the material of the lower layer.

Abstract: A method comprising forming on a common support (6) one or more series of multi-layer electronic devices (covering the areas 2a, 2b respectively), and then separating the electronic devices; wherein the devices comprise one or more organic layers (9), and the method comprises depositing one or more of the organic layers (9) as a respective continuous layer extending at least from one end of the one or more series of devices to an opposite end of the one or more series of devices.

Abstract: A technique comprising: providing a stack of layers defining at least (a) source and drain electrodes, (b) gate electrode, and (c) semiconductor channel of at least one transistor; depositing one or more organic insulating layers over the stack; removing at least part of the stack in one or more selected regions by an ablation technique; depositing conductor material over the stack in at least the one or more ablated regions and one or more border regions immediately surrounding a respective ablated region; and depositing inorganic insulating material over the stack at least in the ablated regions and the border regions to cover the ablated regions and make direct contact with said conductor material in said one or more border regions all around the respective ablated region.

Abstract: A technique of producing a control component for a reflective display device, comprising: forming an array of electronic switching devices; forming over said array of electronic switching devices an insulator region defining a controlled surface topography; and forming on the patterned surface of the insulator region by a conformal deposition technique a substantially planar array of reflective pixel conductors each independently controllable via a respective one of the array of electronic switching devices, wherein each pixel conductor exhibits specular reflection at a range of reflection angles relative to the plane of the array of pixel conductors for a given incident angle relative to the plane of the array of pixel conductors.

Abstract: A method of producing a transistor array, comprising an array of addressing conductors each providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; wherein the method comprises: forming a conductor layer on a support; and displacing a plurality of portions of said conductor layer relative to other portions of said conductor layer to create from said conductor layer at least (i) said array of addressing conductors and an array of drain conductors at said first level, (ii) conductor element islands in transistor channel regions at a second level, and (iii) one or more further conductor elements at a third level.

Abstract: A technique for creating a conductive connection between a contact part (24) of a display back plane (34) and a common electrode (20) of a display front plane (32), comprising the step of compressing a compressible conductive component (30) between the display front plane (32) and the display back plane (34), wherein the method further comprises the step of interposing one or more layers (10, 36) having a low modulus of elasticity not larger than 5 GPa between the contact part (24) and the compressible conductive component (30) prior to the compressing step.

Abstract: A method of producing plural pixellated display devices, each having a first component comprising an array of independently controllable pixel electrodes; and a second component comprising an array of pixel filters comprising different types of pixel filters of differing optical transmission characteristics, each pixel filter being associated with a respective one of said pixel electrodes. The first component has some distortion within the array of pixel electrodes causing a variation in pixel electrode pitch between different regions of the array. The second component is applied to the first component to provide misalignment between an alignment reference position on the first component and an alignment reference position on the second component. An array of pixel filters is formed in a neutral framework having a separation distance between each pixel filter that prevents any pixel filter of the array of pixel filters overlapping with more than one of said pixel electrodes.

Abstract: A method, comprising: generating a vapor of a material from a source of said material comprising a plurality of separate solid pieces of said material supported on a surface of a base in a configuration in which said plurality of solid pieces of said target material are arranged at two or more levels to cover the whole of said surface of said base while providing a gap between adjacent pieces at the same level; and depositing said material from said vapor onto a substrate.

Abstract: A technique of operating a device comprising a patterned conductor layer defining source electrode circuitry and drain electrode circuitry for a plurality of transistors; a semiconductor layer providing a respective semiconductor channel for each transistor between source electrode circuitry and drain electrode circuitry; and gate electrode circuitry overlapping the semiconductor channels of the plurality of transistor devices for switching the semiconductor channels between two or more levels of conductance; wherein the technique comprises using one or more further conductors independent of said gate electrode circuitry to capacitatively induce a reduction in conductivity of said one or more areas of said semiconductor layer outside of said semiconductor channels.

Abstract: The invention relates to an electronic device comprising a limited color display and a method of driving the display. The display has an array of pixels, a driver for driving each of said pixels in said array and a color filter which is aligned with said display whereby each of said pixels is sub-divided into a plurality of sub-pixels of different colors. The method comprises receiving a target image; generating a brightness image for said target image by determining a brightness value for each sub-pixel within said display; generating an output signal from said brightness image by determining an output value for each of said plurality of sub-pixels of different colors within the brightness image; and outputting said output signal to said driver to drive the display.

Abstract: A transistor device comprising: source and drain conductors connected by a semiconductor channel; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein the gate conductor comprises at least one portion overlapping at least part of at least one of said source and drain conductors; and further comprising a patterned insulator interposed between at least part of said at least one of the source and drain conductors and said at least one overlapping portion of said gate conductor so as to reduce capacitive coupling between the said at least one of the source and drain conductors and the gate conductor by more than any reduction in capacitive coupling between the semiconductor channel and the gate conductor.

Abstract: A technique comprising: mounting a device substrate on a processing support, forming one or more electronic elements on the device substrate with the device substrate thus mounted on the processing support; wherein the device substrate comprises an organic support structure, and provides primary protection for the overlying electronic elements against the ingress of a degrading species from a side of the device substrate opposite to the one or more electronic elements.

Abstract: An electronic switching device array encapsulated in an encapsulating structure; wherein said array is exposed to one or more gas pockets between said array and said encapsulating structure.

Abstract: A device comprising an array of transistors; wherein the device comprises an array of first conductors providing either the gate electrodes or the source electrodes for the transistors, and an array of second conductors providing the other of the gate electrodes and the source electrodes for the transistors; wherein the first conductors include conductors that are each associated with a respective group of N rows of the array of transistors; and wherein the columns of transistors include columns of transistors that are associated with a respective set of N second conductors of the array of second conductors, and each second conductor in each set of N second conductors is associated with a respective set of 1/N transistors in the respective column of transistors; wherein N is greater than 1.

Abstract: A method comprising forming on a common support (6) one or more series of multi-layer electronic devices (covering the areas 2a, 2b respectively), and then separating the electronic devices; wherein the devices comprise one or more organic layers (9), and the method comprises depositing one or more of the organic layers (9) as a respective continuous layer extending at least from one end of the one or more series of devices to an opposite end of the one or more series of devices.

Abstract: A device comprising an array of transistors, wherein the device comprises: a first conductor layer at a first level defining a plurality of first conductors providing either source or gate electrodes for said array of transistors; a second conductor layer at a second level defining a plurality of second conductors providing the other of source or gate electrodes for said array of transistors; wherein said second conductor layer further defines routing conductors at one or more locations between said second conductors, each routing conductor connected by one or more interlayer conductive connections to a respective first conductor.

Abstract: A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.