Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Abstract: Server load-balancing operation-related data, such as data associated with a system configured for global server load balancing (GSLB) that orders IP addresses into a list based on a set of performance metrics, is tracked. Such operation-related data includes inbound source IP addresses (e.g., the address of the originator of a DNS request), the requested host and zone, identification of the selected “best” IP addresses resulting from application of a GSLB algorithm and the selection metric used to decide on an IP address as the “best” one. Furthermore, the data includes a count of the selected “best” IP addresses selected via application of the GSLB algorithm, and for each of these IP addresses, the list of deciding performance metrics, along with a count of the number of times each of these metrics in the list was used as a deciding factor in selection of this IP address as the best one.

Abstract: Multiple levels of interrupts to be utilized in a computer system, which allows, for example, an interrupt with an interrupt level associated with an application to be distinct from an interrupt with an interrupt level associated with a kernel. The kernel level interrupt may be handled quickly via its own handler, while the application level interrupt may be handled more slowly. This may be accomplished by first determining if a first-level handler is installed for the interrupt source. If so, then it may be called. Otherwise, the interrupt source may be masked and a second-level handler may be called. Once this second-level handler has completed its tasks, the interrupt source may then be unmasked. Implementations with three or more levels of interrupt are also possible.

Abstract: A system, method and apparatus for supporting enhanced 911 (E911) emergency services, in a data communications network that includes Voice over Internet Protocol (VoIP) telephones. A network system includes a host network communicatively coupled to an E911 database management system, a network access device, and a VoIP telephone communicatively coupled to an input port of the network access device. The network access device is adapted to assign a physical location identifier to an input port, to authenticate the VoIP telephone, wherein the authentication includes receiving a unique device identifier from the VoIP telephone, and to transmit the location identifier and the unique device identifier to the E911 database management system. The E911 database management system is permitted to store the physical location identifier in association with the unique device identifier.

Abstract: An enclosure for operationally retaining a plurality of electronic modules has a housing comprising front, side, upper, lower, and rear walls, and housing enclosing an inner volume. The enclosure has an inner wall running between the side walls and attached to the lower wall. The inner wall is positioned between the front and back walls, and splits the inner volume into a first inner volume and a second inner volume. The inner wall extends from the bottom wall to a height less than that of the height of said top wall, and defines an opening between the first inner volume and the second inner volume. An exhaust vent is disposed through the rear wall of the housing. Openings exist in the housing into the first inner volume. This allows an airflow into the first inner chamber. An environmental flow mechanism, such as a fan, is coupled in proximity to the exhaust vent.

Abstract: The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures.

Abstract: The present invention comprises a shim assembly for supporting a hardware module flush with a bottom side of a printed circuit board. A bottom side of the shim assembly is attached to a top side of the printed circuit board and generally conforms to the shape of a slot in the printed circuit board into which the hardware module is inserted. The shim assembly is of sufficient thickness to fill a gap between the hardware module and the top side of the printed circuit board such that the hardware module does not materially extend past a bottom side of the printed circuit board when inserted in the slot.

Abstract: A multiple key, multiple tiered network security system, method and apparatus provides at least three levels of security. The first level of security includes physical MAC address authentication of a device being attached to the network, such as a device being attached to a port of a network switch. The second level includes authentication of the user of the device, such as user authentication in accordance with the 802.1x standard. The third level includes dynamic assignment of the port to a particular VLAN based on the identity of the user. Failure to pass a lower security level results in a denial of access to subsequent levels of authentication.

Abstract: A phase-locked loop having a phase detector for receiving a feedback signal and an input clock signal having an input clock frequency. The phase detector outputs or produces a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The phase-locked loop also has a loop filter coupled to the phase detector to receive the phase error signal and to output an error correction signal which includes an error correction frequency having a value ranging from about [input clock frequency−(input clock frequency×about 0.00015)] to about [input clock frequency+(input clock frequency×about 0.00015)]. A voltage controlled oscillator is coupled to the loop filter for receiving the error correction signal and to generate an output signal of the phase-locked loop which is indicative of the feedback signal.

Abstract: Methods are provided for enhancing capacity of impaired bone marrow cells to promote angiogenesis when introduced into an ischemic site in a patient by transfecting early attaching cells derived from bone marrow in culture with an angiogenesis promoting transgene. Methods are also provided for utilizing such early attaching cells derived from autologous bone marrow, or media derived from these cells while the cells are grown in culture (which need not be from autologous cells) to deliver angiogenesis-promoting transgenes or proteins to a patient. The transfected early attaching cells, or media derived from these cells while the cells are grown in culture, are introduced into an ischemic tissue, such as the heart, to enhance formation of collateral blood vessels.

Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: A network configuration protocol and algorithm are described which resolve deficiencies with existing protocols. A large network having many bridges may be built as a combination of smaller networks, many of which may each be arranged in a ring topology. Each ring may be monitored by a single master bridge regularly sending control packets, and each other bridge in the ring does not make decisions with respect to its status. A loop free topology is achieved by selectively blocking and unblocking data traffic in one of the ring ports of the single master bridge for the ring, while all other bridges in the ring keep their ports in non-blocked states. In multiple ring topologies, each ring has a single master bridge which chooses one of its ports to be blocking.

Abstract: A phase-locked loop having a phase detector for receiving a feedback signal and an input clock signal having an input clock frequency. The phase detector outputs or produces a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The phase-locked loop also has a loop filter coupled to the phase detector to receive the phase error signal and to output an error correction signal which includes an error correction frequency having a value ranging from about [input clock frequency−(input clock frequency×about 0.00015)] to about [input clock frequency+(input clock frequency×about 0.00015)]. A voltage controlled oscillator is coupled to the loop filter for receiving the error correction signal and to generate an output signal of the phase-locked loop which is indicative of the feedback signal.

Abstract: A method and apparatus for thermally regulating a computing system responsive to a sensor failure is envisioned. The system has a fan. The system also has a sensor placed in the casing that is responsive to an environmental condition. A first circuit is coupled to the sensor and the fan, and is able to regulate the rotational speed at which the fan operates. The first circuit operates the fan at an increased rotational speed upon an indication of a failure of the sensor.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A network switch includes a plurality of cross points each having a plurality of ports, a switching fabric that routes traffic between the plurality of cross points, and an arbitrator that arbitrates the traffic in a cut-through mode for packets larger than a predetermined size, and in a store and forward mode for packets smaller than the predetermined size.