Patents Assigned to Freescale Semiconductor
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Patent number: 9514945Abstract: A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides. The deuterated hydride can be used to form an amorphous semiconductor material that is annealed to form nanoparticles to be incorporated into the charge-storing layer.Type: GrantFiled: December 12, 2014Date of Patent: December 6, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Cheong Min Hong, Euhngi Lee
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Patent number: 9515635Abstract: The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.Type: GrantFiled: July 23, 2015Date of Patent: December 6, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Michael A. Sadd, Anirban Roy
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Patent number: 9513653Abstract: An apparatus and corresponding method are provided to control a switched current circuit by switching the switched current circuit into an ON-state, waiting an amount of waiting an amount of time tB after the current within the switched current circuit increases above a current threshold, and switching the switched current circuit into an OFF-state after waiting the time tB. Further, a duration of time tA1 between switching the switched current circuit in the OFF-state and the point at which the current within the switched current circuit decreases below the current threshold is determined, and the method includes waiting a time tA2 after the current within the switched current circuit decreased below the current threshold, the time tA2 based at least in part on the time tA1, after which the switched current circuit is switched into the ON-state.Type: GrantFiled: September 15, 2014Date of Patent: December 6, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Steven Everson, David Putti
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Patent number: 9508622Abstract: A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.Type: GrantFiled: April 28, 2011Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Leo M. Higgins, III
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Patent number: 9506756Abstract: A microelectromechanical systems (MEMS) device includes at least two rate sensors (20, 50) suspended above a substrate (30), and configured to oscillate parallel to a surface (40) of the substrate (30). Drive elements (156, 158) in communication with at least one of the rate sensors (20, 50) provide a drive signal (168) exhibiting a drive frequency. One or more coupling spring structures (80, 92, 104, 120) interconnect the rate sensors (20, 50). The coupling spring structures enable oscillation of the rate sensors (20, 50) in a drive direction dictated by the coupling spring structures. The drive direction for the rate sensors (20) is a rotational drive direction (43) associated with a first axis (28), and the drive direction for the rate sensors (50) is a translational drive direction (64) associated with a second axis (24, 26) that is perpendicular to the first axis (28).Type: GrantFiled: March 15, 2013Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Andrew C. McNeil, Yizhen Lin
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Patent number: 9508397Abstract: An operating voltage and reference current are adjusted in a memory device. At least a portion of an array of memory cells is preconditioned to an erased state using an erase verify voltage on word lines coupled to the memory cells and a first reference current in sense amplifiers coupled to bit lines for the array. A test reference current is set for the sense amplifiers. A bitcell gate voltage is set on the word lines to a present overdrive voltage. The at least a portion of the array is read. If any of the memory cells in the at least a portion of the array are read as being programmed, the present overdrive voltage is increased until none of the memory cells in the at least a portion of the array are read as being programmed.Type: GrantFiled: December 3, 2015Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Richard K. Eguchi, Thomas Jew, Craig T. Swift
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Patent number: 9507373Abstract: An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.Type: GrantFiled: July 4, 2013Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Hubert Bode, Dirk Wendel
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Patent number: 9507680Abstract: A system for verifying register information includes a design database containing a description of the electronic system, a register description database containing register information relating to the electronic system, a customization information module for storing a customization information extracted from the design database and a simulator which is arranged to execute verification stimuli in accordance with at least one check function and to generate a verification result. Verification stimuli are generated by combining register information with customization information. A mismatch between the expected and actual register implementation is recorded and the register in question identified. This permits corrections to be applied as appropriate to the document database or to the register description database. The corrected register description database may be used in a document generation process to produce an up-to-date reference manual for the electronic system.Type: GrantFiled: March 24, 2014Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Michael Rohleder, Glen Nicholas Mithran Evans, Bridget Catherine Hooser, Carmen Klug-Mocanu
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Patent number: 9506979Abstract: An integrated circuit having normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal (204) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.Type: GrantFiled: April 2, 2014Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventors: William E. Edwards, John M. Hall
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Patent number: 9508845Abstract: An LDMOS device implements a substrate having a buried isolation layer, a first well region that incorporates two stacked sub-regions to provide a PN junction with a RESURF effect, and a second well region laterally offset from the first well region. A source region is formed in one of the well regions and a drain region is formed in the other well region. An extension region is disposed immediately adjacent to the first well region and laterally distal to the second well region. An extension biasing region is formed at least partially within the extension region, and is separated from the first well region by a portion of the extension region. One or more metallization structures electrically couple the extension biasing region to the one of the source/drain region in the second well region. A gate structure at least partially overlaps both well regions.Type: GrantFiled: August 10, 2015Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Xin Lin, Hongning Yang, Jiang-Kai Zuo
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Patent number: 9509332Abstract: A sigma-delta (??) analog-to-digital converter (ADC) comprises a main ?? modulator configured to receive an analog input signal at a main ?? modulator input and to provide a main digital output signal representative of the analog input signal and an auxiliary ?? modulator configured to receive an auxiliary input signal at an auxiliary ?? modulator input and to provide an auxiliary digital output signal, wherein the ?? ADC comprises a shared integrator stage, the shared integrator stage is configured to be used by the main ?? modulator and the auxiliary ?? modulator, wherein, alternatingly, the shared integrator stage is selectively communicatively coupled to receive the analog input signal when configured to be used by the main ?? modulator and selectively communicatively coupled to receive the auxiliary input signal when configured to be used by the auxiliary ?? modulator.Type: GrantFiled: November 6, 2015Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Douglas A. Garrity, Mariam Hoseini, Mark J. Stachew
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Patent number: 9509310Abstract: A driver circuit configured to produce a pair of output signals from a pair of input signals. The proposed solution brings improvements over conventional LVDS and subLVDS driver circuits because it enables the use of a single driver circuit (also known as “buffer”) which is compliant with both LVDS and subLVDS transmission standards. This allows flexibility with MCUs for instance the automotive industry. Further, proposed solution has the advantage of saving die size in comparison to a solution where two buffers would have been used for different transmission standards. Further, high speed transmission rate is maintained since transmission is performed for one standard at the time. An integrated circuit, a printed circuit and a data processing circuit are also claimed.Type: GrantFiled: February 25, 2016Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Birama Goumballa, Cristian Pavao-Moreira, Didier Salle
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System and method for on-die voltage difference measurement on a pass device, and integrated circuit
Patent number: 9500679Abstract: A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.Type: GrantFiled: July 19, 2012Date of Patent: November 22, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Michael Priel, Leonid Fleshel, Sergey Sofer -
Patent number: 9500740Abstract: A receiver circuit, comprises an input balun circuit comprising a balanced balun output and being capable of receiving RF signals, an input amplification circuit comprising a balanced amplifier input and a balanced amplifier output, a single balanced in-phase mixing circuit comprising a first unbalanced RF mixer input and a balanced in-phase mixing frequency input, and a single balanced quadrature mixing circuit comprising a second unbalanced RF mixer input and a balanced quadrature mixing frequency input. The balanced amplifier input is connected to the balanced balun output, a first terminal of the balanced amplifier output is connected to provide an amplified RF signal to the first unbalanced RF mixer input and a second terminal of the balanced amplifier output is connected to provide a phase-shifted amplified RF signal to the second unbalanced RF mixer input.Type: GrantFiled: October 27, 2011Date of Patent: November 22, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Saverio Trotta
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Patent number: 9503295Abstract: A drive-mode oscillator module generates at least one proof-mass drive signal for use within a micro-electro-mechanical system (MEMS) device. The drive-mode oscillator module comprises at least one gain control component arranged to receive at least one proof-mass motion measurement signal, and to generate a digital modulation control signal based at least partly on the at least one proof-mass motion measurement signal, and at least one modulation component arranged to receive the digital amplitude modulation control signal, and to output at least one proof-mass drive signal. The at least one modulation component is arranged to digitally modulate the at least one proof-mass drive signal based at least partly on the received digital amplitude modulation control signal.Type: GrantFiled: November 6, 2012Date of Patent: November 22, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Laurent Cornibert, Hugues Beaulaton, Thierry Cassagnes, Gerhard Trauth
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Patent number: 9500669Abstract: A system (40) for calibrating an inertial sensor (20) includes a power source (42), a frequency measurement subsystem (44, 48), and a gain determination subsystem (52). A calibration process (110) using the system (40) entails applying (116) a bias voltage (66) to the inertial sensor (20), measuring (114) a drive resonant frequency (46), and measuring (118) a sense resonant frequency (50) of the inertial sensor (20) produced in response to the bias voltage (66). A gain value (32) is determined (124) for calibrating (144) the inertial sensor (20) using a relationship (140) between the sense resonant frequency (50) and the bias voltage (66) without imposing an inertial stimulus on the inertial sensor (20).Type: GrantFiled: January 15, 2014Date of Patent: November 22, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Margaret L. Kniffin, Andrew C. McNeil
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Patent number: 9501443Abstract: A differential line driver circuit comprising a plurality of driver stages is described. Each driver stage is operably coupled to at least one output of the line driver circuit and arranged to receive at least one control signal and to drive at least one output signal on the at least one output of the line driver circuit in accordance with the at least one control signal received thereby. The line driver circuit further comprises at least one delay component arranged to receive the at least one control signal, and to sequentially propagate the at least one control signal to the driver stages with time delays between the propagation of the at least one control signal to sequentially adjacent driver stages.Type: GrantFiled: June 27, 2012Date of Patent: November 22, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Matthijs Pardoen
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Patent number: 9502363Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.Type: GrantFiled: March 24, 2014Date of Patent: November 22, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Michael B. Vincent, Trung Q. Duong, Zhiwei Gong, Scott M. Hayes, Alan J. Magnus, Douglas G. Mitchell, Eduard J. Pabst, Jason R. Wright, Weng F. Yap
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Patent number: 9501081Abstract: A proportional-to-absolute-temperature (“PTAT”) circuit includes a bias component; first, second, third, and fourth transistors; an output transistor; and a first resistive component. A first terminal of the bias component is coupled to a voltage supply node. The first and second transistors are connected to a second terminal of the bias component. The third and fourth transistors have different current densities. The first transistor is coupled to the third transistor. The second transistor is coupled to the fourth transistor. The fourth transistor and the first resistive component are coupled to a voltage common node. The output transistor has a control terminal coupled to the second and fourth transistors, a first current terminal connected to an output node, and a second current terminal coupled to the third transistor and the first resistive component. The PTAT circuit is configured to generate at least a portion of a PTAT current at the output node.Type: GrantFiled: December 16, 2014Date of Patent: November 22, 2016Assignee: Freescale Semiconductor, Inc.Inventor: John M. Pigott
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Patent number: 9499397Abstract: Microelectronic packages and methods for producing microelectronic packages are provided. In one embodiment, the method includes bonding a first Microelectromechanical Systems (MEMS) die having a first MEMS transducer structure thereon to a cap piece. The first MEMS die and cap piece are bonded such that a first hermetically-sealed cavity is formed enclosing the first MEMS transducer. A second MEMS die having a second MEMS transducer structure thereon is further bonded to one of the cap piece and the second MEMS die. The second MEMS die and the cap piece are bonded such that a second hermetically-sealed cavity is formed enclosing the second MEMS transducer. The second hermetically-sealed cavity contains a different internal pressure than does the first hermetically-sealed cavity.Type: GrantFiled: March 31, 2014Date of Patent: November 22, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Philip H. Bowles, Stephen R. Hooper