Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having multiple vertically-stacked inertial transducer elements (101B, 110D) formed in different layers of a multi-layer semiconductor structure (100) and one or more cap devices (200, 300) bonded to the multi-layer semiconductor structure (100) to protect any exposed inertial transducer element from ambient environmental conditions.

Abstract: A method of provisioning an integrated circuit with decoupling capacitance includes identifying in an initial design of the integrated circuit lacking decoupling elements, a standard cell instance satisfying a transient power or frequency switching criteria. Based on a transient power characteristic of the standard cell instance, a decoupling capacitance requirement for the standard cell instance is determined. The decoupling capacitance requirement indicates a capacitance sufficient to bring the standard cell instance into compliance with a stability constraint on a supply voltage node of the standard cell instance. A decoupling capacitor satisfying the decoupling capacitance requirement is provisioned by appending an appropriate sized decap transistor having one or more gate electrode elements to the standard cell instance.

Abstract: Apparatuses, methods, and systems are configured to perform unambiguous parameter sampling in a heterogeneous multi-core or multi-threaded environment by masking one or more thread requests; and, in response to bus activity ceasing for the one or more masked thread requests and completing any routine being processed for the one or more masked threads, processing a command by executing at least one of a command routine or a command thread, wherein the command routine or the command thread reads the parameter using thread atomicity with deterministic synchronization. One or more thread requests may be selected for masking by monitoring thread activity for each of a plurality of threads.

Abstract: A packaged integrated circuit (IC) device having a heatsink mounted onto an IC die, itself mounted onto a die pad, is assembled using a lead frame having tie bars that deflect during an encapsulation phase of the device assembly, which enables the die pad, the die, and the heatsink to move relative to the lead frame support structure when compressive force is applied by the molding tool. This movement results in negligible relative displacement between the heatsink and the die during encapsulation, which reduces the probability of physical damage to the die. Each tie bar has a number of differently angled sections that enable it to deflect when compressive force is applied to it.

Abstract: A mixed mode integrated circuit, a method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and a method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit are provided. The mixed mode integrated circuit 100 comprises in addition to a clock network 110 an integrated test clock signal generator 140 to generate test clock signals that are provided via controllable multiplexers 150, 160 to an analog and digital sub-circuitry, respectively, of the mixed-mode integrated circuit. The test clock signals are generated on basis of an input test clock signal having a controllable frequency. The clock network generates clock signals for the sub-circuitries that are used by the sub-circuitries under normal operational conditions. The controllable multiplexers provide either the test clock signal to a specific sub-circuitry or a clock signal received from the clock network.

Abstract: A microelectromechanical systems (MEMS) die includes a substrate having a first substrate layer, a second substrate layer, and an insulator layer interposed between the first and second substrate layers. A structure is formed in the first substrate layer and includes a platform upon which a MEMS device resides. Fabrication methodology entails forming the MEMS device on a front side of the first substrate layer of the substrate, forming openings extending through the second substrate layer from a back side of the second substrate layer to the insulator layer, and forming a trench in the first substrate layer extending from the front side to the insulator layer. The trench is laterally offset from the openings. The trench surrounds the MEMS device to produce the structure in the first substrate layer on which the MEMS device resides. The insulator layer is removed underlying the structure to suspend the structure.

Abstract: A method includes applying a compressive force against MEMS structures at a front side of a MEMS wafer using a protective material covering at least a portion of the front side of the MEMS wafer. The method further includes concurrently dicing through the protective material and the MEMS wafer from the front side to produce a plurality of MEMS dies, each of which includes at least one of the MEMS structures. The protective material is secured over the front side of the MEMS wafer to apply pressure to the protective material, and thereby impart the compressive force against the MEMS structures to largely limit movement of the MEMS structures during dicing. A tack-free surface of the protective material enables its removal following dicing.

Abstract: A semiconductor device comprises a power transistor and a sense transistor. The power transistor conducts a power transistor current. The sense transistor conducts a sense transistor current substantially proportional to of the power transistor current. The power transistor and the sense transistor have drain source and a gate terminals, of which those of the sense transistor are arranged to be biased to those of the power transistor, respectively. The power transistor and the sense transistor each comprise: an inner region of type P?; an N-type buried layer; an N-type isolating barrier surrounding the inner region partially; an N-type source region in the inner region; an N-type drain region in the inner region. A barrier-to-drain connector connects the isolating barrier to the drain region, the one of the sense transistor has an electrical resistance which is higher than the resistance of the barrier-to-drain connector of the power transistor.

Abstract: A method of making a semiconductor device forms anchors for one or more layers of material. The method includes depositing a first layer of material on a substrate, applying a mask over the first layer of material to mask nanoparticle-sized areas of the first material, removing portions of the first layer of material to form a first set of recesses around the nanoparticle-sized areas of the first material, depositing a second layer of material in the recesses and over the nanoparticle-sized areas so that a second set of recesses is formed in a top surface of the second layer of material, and forming a component of the semiconductor device over the second layer of material. Material of a bottom surface of the component is included in the second set of recesses.

Abstract: In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. The method includes resuming execution in delayed lockstep of the redundant computing modules in response to the handling of the error.

Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.

Abstract: A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.

Abstract: The present application relates to an apparatus for detecting software interference and the method of operating thereof. A processor and at least one shared resource form a computing shell to execute a first, functional safety critical application and at least one second application in time-shared operation. One or more performance counters are provided to adjust a counter value in response to a performance related event. A reference value storage stores one or more threshold values, each of which is associated with one of the performance counters. A comparator receives the performance counter values, compares the performance counter values with the respective threshold values and generates at least one comparison signal in response to results of the comparisons. An interference indication generator receives the at least one comparison signal and generates at least one interference indication in response to the at least one received comparison signal.

Abstract: A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

Abstract: A microelectromechanical systems (MEMS) die includes a substrate having a recess formed therein and a cantilevered platform structure. The cantilevered platform structure has a platform and an arm extending from the platform, wherein the platform and arm are suspended over the recess. The arm is fixed to the substrate and is a sole attachment point of the platform to the substrate. A MEMS device resides on the platform. Fabrication methodology entails forming the recess in the substrate, with the recess extending inwardly from a surface of the substrate, and attaching a structural layer over the recess and over the surface of the substrate. The MEMS device is formed on the structural layer and the structural layer is removed around a perimeter of the platform and the arm to form the cantilevered platform structure.

Abstract: A circuit arrangement for Logic Built-In Self-Test (LBIST) includes a clock source configured to generate a system clock, a first clock division circuitry configured to derive a first punched-out clock and a plurality of scan chains operable at the first punched-out clock. Each scan chain has an associated output circuitry responsive to a leading edge of the first punched-out clock. The circuit arrangement includes a second clock division circuitry configured to derive a second punched-out clock. The second punched-out clock has a delay of one or more system clock periods relative to the first punched-out clock. A compacting logic is configured to compact signals received from the scan chains. A sequential retiming element connects the compacting logic to an input circuitry of a MISR. The sequential retiming element is responsive to a trailing edge of the second punched-out clock. The input circuitry is responsive to a leading edge of the second punched-out clock.

Abstract: A programmable buffer system includes a plurality of programmable resources. Each of the programmable resources includes, in an unconfigured state, a buffer with multiple entries, an input multiplexer, and an output multiplexer. Configuration information registers specify whether each of the programmable resources is configured as one of a group consisting of: a logic block, a shift register, and a state record, and which of a plurality of timer signals is to be provided to each of the plurality of programmable resources.

Abstract: A system and method of accelerating sparse matrix operations in full accuracy simulation of a circuit includes determining repetitive blocks of the circuit, determining a set of values of a current block, determining whether the state of the current block is sufficiently close to the state of a stored block solution when the corresponding values are within a predetermined error range, and performing a reduced computation using the stored block solution to provide a solution for the current block when the states are sufficiently close to each other. The reduced computation includes retrieving previously stored solutions and performing substantially simplified matrix and vector operations while maintaining accuracy of the solution. Reduced precision versions of the values may be used to generate a hash index used to store the block solutions. Stored redundant device information may also be used to simplify device solutions in a similar manner.

Abstract: There is provided an energy consumption meter device (1) comprising the processor (8) arranged to receive input data from the sampling unit. The processor calculates at a calculation step [n] an energy contribution value using ?E using a sampled voltage value and a sampled current value. The processor will calculate an energy value E[n] using a reminder value which was calculated at a previous calculation step [n?1]. The processor will then calculate a relative delay Td? using the threshold value, the reminder value and the energy value, and generate an output pulse at an output time tpulse which is delayed for the relative delay Td? with respect to the calculation time step[n]. By delaying the output pulse with a value which is a closest proximity of Td, the cycle-by-cycle jitter is less or equal to the clock frequency of the timer tclk.

Abstract: An integrated circuit comprises a transistor body control circuit for controlling a body of a bidirectional power transistor. The transistor body control circuit comprises switches connected between a body terminal and a first current terminal, with a control terminal for controlling the current flowing through the switch. The control terminal of the switch is connected to alternating current, AC capacitive voltage divider. The AC capacitive voltage dividers are connected to the control terminals and arranged to control the switches to switch the voltage of the body terminal as a function of the voltage between the first current terminal and the second current terminal. The integrated circuit further comprises a bi-directional power transistor connected to the transistor body control circuit.