Abstract: A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code word polynomials, where d is the number of unique code word polynomials. The computed set of 2d-1 unique branch metrics is stored in a memory. Path metrics are then calculated, based on the stored set of 2d-1 unique branch metrics. A decoded data symbol sequence is generated based on the computed path metrics.

Abstract: A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the semiconductor substrate and adjacent the control electrode to form a channel within the semiconductor substrate. The second current electrode has a second predetermined semiconductor material that is different from the first predetermined semiconductor material. The first predetermined semiconductor material is chosen to optimize bandgap energy of the first current electrode, and the second predetermined semiconductor material is chosen to optimize strain of the channel.

Abstract: A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.

Abstract: An audio amplifier includes a digital signal processor (DSP) that contains a noise shaping quantizer having an integrating error amplifier. The integrating error amplifier contains integrators connected in a feedback loop, a summer supplied with an output of each of the integrators, and a saturation function module producing a saturation function. A multiplier is disposed between each pair of adjacent integrators. The multiplier receives a signal from one of the adjacent integrators and the saturation function and supplies a signal to the other of the adjacent integrators. The saturation function decreases the effect of all of the integrators except an integrator to which an input signal to the integrating amplifier is supplied using an input signal to and/or an output signal from the noise shaping quantizer. This permits the duty ratio of the output signal from the noise shaping quantizer to extend from 0% to 100%.

Abstract: Methods and apparatus are provided for preparing sensing fingers for use in a highly integrated accelerometer. The method includes steps for forming a tungsten/tungsten silicide coating on a silicon finger. The tungsten/tungsten silicide coating adds mass to the silicon finger. The method includes steps of forming silicon fingers from layers of silicon, oxides, and capping material. The silicon fingers are then exposed to tungsten containing gases under conditions to promote the formation of a tungsten silicide seed layer on the exposed silicon surfaces. The tungsten layer is then grown to a desired thickness through a growth step. The coated silicon fingers display improved resistance to stiction as compared to uncoated silicon fingers.

Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Abstract: A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

Abstract: A magnetic tunnel junction (MTJ), which is useful in magnetoresistive random access memories (MRAMs), has a free layer which is a synthetic antiferromagnet (SAF) structure. This SAF is composed of two ferromagnetic layers that are separated by a coupling layer. The coupling layer has a base material that is non-magnetic and also other materials that improve thermal endurance, control of the coupling strength of the SAF, and magnetoresistance ratio (MR). The preferred base material is ruthenium and the preferred other material is tantalum. Furthering these benefits, cobalt-iron is added at the interface between the tantalum and one of the ferromagnetic layers. Also the coupling layer can have even more layers and the materials used can vary. Also the coupling layer itself can be an alloy.

Abstract: A process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate and forming a trench within the substrate. The process can also include forming a second set of discontinuous storage elements within the trench. The process can further include forming a first gate electrode within the trench, wherein a discontinuous storage element lies between the first gate electrode and a wall of the trench. The process can still further include removing a part of the second set of discontinuous storage elements and forming a second gate electrode over the first gate electrode. After forming the second gate electrode, substantially none of the second set of discontinuous storage elements lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and the primary surface of the substrate.

Abstract: The present invention relates generally to interfacing a processor with at least one coprocessor. One embodiment relates to a processor having a set of broadcast specifiers which it uses to selectively broadcast an operand that is being written to a register within the processor to a coprocessor communication bus. Each broadcast specifier may therefore include a broadcast indicator corresponding to each general purpose register of the processor. An alternate embodiment may also use the concept of broadcast regions where each broadcast region may have a corresponding broadcast specifier where one broadcast specifier may correspond to multiple broadcast regions. Alternatively, in one embodiment, the processor may use broadcast regions independent of the broadcast specifiers where the coprocessor is able to alter its functionality in response to the current broadcast region.

Abstract: A memory and a method for programming a memory device are discussed. The method comprises selecting a cell to program, wherein the cell is coupled to a bit line, applying a first programming pulse, wherein the first programming pulse comprises applying a first voltage to the bit line, verifying if the cell is programmed after applying the first programming pulse, and applying a second programming pulse to the bit line after applying the first programming pulse if the cell is not programmed after applying the first programming pulse, wherein second programming pulse comprises applying a second voltage to the bit line, wherein the second voltage is different than the first voltage.

Abstract: An automatic gain control (AGC) method and circuit (10) within a receiver uses a digital state machine (26) to implement the AGC function. independent from interaction with a host processor (36) and for multiple modulation protocols without duplicating circuitry. Modulation protocol and parameters for any of various gain responses are stored in a register (29). Multiple states, each corresponding to a predetermined range of RF input signal strength, are stored in the register. Each state contains parameters that determine a gain control signal for controlling a variable gain amplifier (16). The states are independent and may be selectively disabled to create asymmetric responses. Within any state, an adaptable number of iterations may be set to implement a different update rate or step size after a predetermined number of closed loop gain change iterations has not resulted in a transition to a state that represents a desired output gain.

Abstract: Biasing a transistor connected to a voltage converter, the method includes: (i) providing at least one bias voltage to at least one well of at least one transistor of a test circuitry; (ii) measuring at least one parameter of a test circuitry representative of at least one characteristic of the transistor and of at least one characteristic of the voltage converter; (iii) altering at least one bias voltage and repeating the stages of providing and measuring until a predefined control criteria is fulfilled; and (iv) providing a voltage bias to a well of the transistor in response to the measurements.

Abstract: A method is provided for reducing a DC bias in a receiver. This method includes isolating a second circuit portion from a first circuit portion (535) and determining a second DC bias correction value for the second circuit portion that will eliminate a second DC bias at the isolated second circuit portion (540). The second circuit portion is then connected to the first circuit portion (550) and a bias-maximizing code word is generated at the first circuitry (505). A first DC bias correction value is then determined that will eliminate a first DC bias at the first circuit portion (555). The bias-maximizing code word is formed such that: a first integrated value of a first half of the bias-maximizing code word has a positive value, and a second integrated value of a second half of the bias-maximizing code word over half of the code word length has a negative value.

Abstract: A method and an apparatus are provided for mitigating spectral lines in a wireless signal. First a code word is generated that is made up of a plurality of binary or ternary encoded pulses. Then a plurality of code-word-modulated wavelets are generated in response to the code word. These wavelets can be Gaussian monopulses, repeated cycles of a sine wave, or other shaped impulse signals. The plurality of code-word-modulated wavelets are then modulated with a bit of transmit data to form a plurality of data-modulated wavelets. This modulation serves to whiten the signals since the transmit data is effectively random. Finally, the plurality of data-modulated wavelets are transmitted to a remote device.

Abstract: A method is provided for operating a network device (340) in a wireless network (100). This method includes: joining the wireless network; transmitting a probe command (600) after joining the wireless network, the probe command being addressed to a reserved device identifier; listening for an acknowledgement to the probe command from an orphan device (360); sending a management transmission to a network controller (310) requesting the creation of a child network if an acknowledgement to the probe command is received; receiving a controller transmission from the network controller granting permission to create the child network; creating the child network; and allowing an outside device to join the child network.

Abstract: An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.

Abstract: A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.

Abstract: A method of packaging an integrated circuit die (12) includes the steps of loading an array of soft conductive balls into recesses formed in a platen and locating the platen in a first part of a mold cavity. A second part of the mold is pressed against the balls to flatten a surface of the balls. A first mold compound then is injected into the mold cavity such that the mold compound surrounds exposed portions of the balls. The balls are removed from the platen and a first side of an integrated circuit die is attached to the balls such that the die is surrounded by the balls. Die bonding pads on a second side of the die are electrically connected to respective ones of the balls surrounding the die, and then the die, the electrical connections, and a top portion of the conductive balls is encapsulated with a second mold compound. The result is an encapsulated IC having a bottom side with exposed balls.