Abstract: A method includes receiving, at an interconnect, a first transaction request from a first requesting module. The first transaction request includes a request to utilize at least one system resource accessible via the interconnect. The method further includes determining potential interferences at the interconnect expected to occur as a result of a utilization of the at least one system resource by the first requesting module and initiating processing of the first transaction request at the interconnect. The method additionally includes authorizing processing of a second transaction request from a second requesting module during the processing of the first transaction request based on the determined potential interferences.

Abstract: An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided.

Abstract: A low drop-out DC voltage regulator for regulating a voltage from a DC power supply applied to a load at an output of the regulator and comprising a pass device for controlling flow of current from the power supply to the load so as to control the output voltage at the regulator output, and a feedback loop for controlling the pass device. The feedback loop comprises a resistive feedback path and a capacitive feedback path that includes a feedback capacitive element in series, and comparator means responsive to signals from the feedback paths for applying to the pass device an error signal that is a function of the value of the output voltage relative to a nominal value so as to control the output voltage.

Abstract: A fuse circuit and an electronic circuit for outputting a signal in accordance with the breakage of fuses even when the resistances of the broken fuses differ, reducing leak currents, and lowering power consumption. The fuse circuit includes a plurality of fuse lines, each including a fuse connected to a low-potential ground line and to a high-potential line via a MOS transistor and a constant current source. The fuse lines also each includes an inverter having an input terminal connected between the MOS transistor and constant current source. A reference circuit is connected in parallel to the fuse lines and includes a current source, a transistor, and a resistor connected in series. The transistor of the reference circuit has an input terminal connected to its control terminal and to the control terminal of each MOS transistor.

Abstract: The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.

Abstract: A low drop-out voltage regulator having a pass device (Mp), an error amplifier (M1-M51) and a double regulation loop including DC feedback loop (R1, R2) and an AC feedback loop (Rf, Cf) including a high pass filter (Cf). Combining these two loops creates an ultra low frequency internal pole which makes the regulator stable substantially independent of the output bypass capacitor's value. This provides the following advantages: allows the use of very low bypass capacitors; allows to extend the PSRR frequency behavior; allows an increase in the regulator's efficiency (reduced power consumption on heavy loads).

Abstract: In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1?xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1?xAs channel layer (512) is formed over the AlxGa1?xAs layer (506). An AlxGa1?xAs layer (518) is formed over the InxGa1?xAs channel layer (512), and the AlxGa1?xAs layer (518) has a second doped region formed therein. A GaAs layer (520) having a first recess is formed over the AlxGa1?xAs layer (518). A control electrode (526) is formed over the AlxGa1?xAs layer (518). A doped GaAs layer (524) is formed over the undoped GaAs layer (520) and on opposite sides of the control electrode (526) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device (500) maintains linear operation over a wide temperature range.

Abstract: A circuit for protecting an electronic device including a differential nulling avalanche clamp circuit (200, 300) and method of using the circuit in an electronic system (100) to limit radio frequency overdrive. The electronic system (100) includes a surge clamp (130) coupled to dissipate an electrical surge effect of a first frequency from a noise sensitive node (140) and a ring wave clamp (120) coupled to dissipate an electrical surge effect of a second frequency from the noise sensitive node (140). The ring wave clamp circuit (200, 300) includes a first bipolar junction transistor (210, 310), a second bipolar junction transistor (220, 320) coupled to the first bipolar junction transistor (210, 310), and a resistive circuit (230, 330, 340) coupled to the first and second bipolar junction transistors (210, 220, 310, 320).

Abstract: In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The field plate (40) comprises a plurality of connection locations (47) and a plurality of electrical connectors (45) connecting said plurality of connection locations (47) to a potential.

Abstract: A level shifter circuit, which includes a Schmitt trigger function, shifts voltage of a high level signal into a low voltage and shifts a signal at an intermediate value of an input voltage. The level shifter circuit includes an input terminal connected to low and high voltage circuits. The low voltage circuit outputs a low drive voltage or ground voltage. The high voltage circuit outputs a high drive voltage or a high reference voltage, which is supplied to an RS latch circuit via a potential adjustment circuit at a level equal to an output potential at the low voltage circuit. The RS latch circuit uses the output of the potential adjustment circuit when the input voltage shifts to a high level and uses the output of the low voltage circuit when the input voltage shifts to a low level.

Abstract: A method includes determining, at a first requesting component of an integrated circuit device, a first key value based on a first set of one or more bits of a first address associated with a first access request of the first requesting component. The method further includes transmitting the first key value from the first requesting component to a resource component of the integrated circuit device. The method also includes determining, at the resource component, an authorization of the first access request based on the first key value and a second set of one or more bits of the first address.

Abstract: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.

Abstract: A device and method for temperature compensation of an electronic device are disclosed. The device includes a temperature bias controller with a temperature sensor. A bias signal based upon a signal from the temperature sensor is provided to a first gate of a multiple fin gate field effect transistor (multigate FinFET) transistor of a functional block. A second gate of the multigate FinFET transistor receives a control signal to control its operation within the functional block. In this configuration the first gate of the multigate FinFET transistor can be used for temperature compensation while the second gate is used for functional operation of the transistor. Specific embodiments of the present disclosure will be better understood with respect to the figures.

Abstract: Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

Abstract: A method of fabricating a semiconductor storage cell that includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals. Spacer control gates are located in the trenches adjacent to the charge storage stacks on the trench sidewalls. The trench depth exceeds the spacer height so that a gap exists between a top of the spacers and the top of the substrate. A continuous select gate layer overlies the first trench. The gap facilitates ballistic programming of the DSEs adjacent to the gap by accelerating electrons traveling substantially perpendicular to the trench sidewalls. The storage cell may employ hot carrier injection programming to program a portion of the DSEs proximal to the source/drain regions.

Abstract: An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage.

Abstract: A method of reducing an inter-atomic bond strength in a substance includes the steps of: providing a target material (110, 910, 1210, 1260, 1410, 1460); exposing the target material to a particle flood (140); and annealing the target material while exposing the target material to the particle flood. As an example, the target material can be a collection of non-activated dopant atoms within a semiconducting material. As another example, the target material can be a semiconducting material in an amorphous form. In a different embodiment of the invention an electrically conducting material (950, 1250, 1270, 1450, 1470, 1480) is used as an electron source rather than a particle flood, and an electrically conducting diffusion barrier (940) is placed between the electrically conducting material and the target material.

Abstract: An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have a second channel length extending along a second line. The first line and the second line can intersect at an angle having a value other than any integer multiple of 22.5°. In a particular embodiment, the first transistor can include a pull-up transistor, and the second transistor can include a pass gate or pull-down transistor. A process can be used to form semiconductor fins and conductive members, which include gate electrode portions, to achieve the electronic device including the first and second transistors.

Abstract: A method and apparatus is provided for prefetching in a data processing system (10). The data processing system (10) has a bus master (14) and a memory controller (16) coupled to a bus (12). A memory (18) is coupled to the memory controller (16). In the data processing system (14) an address is driven onto the bus (12). Before the address is qualified, data corresponding to the address is prefetched. Prefetching the data before the address is qualified allows prefetches to be accomplished sooner.

Abstract: The invention relates to debug circuitry (20) and more particularly to a method and apparatus for providing security for debug circuitry (20). In one embodiment, a plurality of non-volatile elements (38) are used in providing selective disabling and re-enabling of at least a portion of the debug circuitry (20). Authentication may also be used. The present invention may use any debug interface, including standard debug interfaces such as the JTAG debug interface defined by the IEEE.