Abstract: A method is provided for acquiring incoming signals in a wireless network device. This method uses three different types of preamble: a normal preamble, a short preamble, and a long preamble. One of these preambles will be used as a default preamble. Then, depending upon signal parameters, the device can change from one preamble to another, trading off data transmission speed and acquisition time to achieve the maximum data transmission speed by using the minimum acquisition time. These signal parameters could be signal strength, the number of packet retransmissions the device must request, or any other metric that is required. And thresholds will vary with the quality of service.

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: A system and method is provided for detection of a human body fall event. The fall detection system (100, 200) includes a monitoring unit (102, 202), including a plurality of accelerometers (106, 206), a processor (108, 208) and a wireless transmitter (110, 210). The plurality of accelerometers (106, 206) provide acceleration measurements to the processor (108, 208), the measurements describing the current acceleration of the person wearing the monitoring unit (102, 202) in all directions. The processor (108, 208) receives the acceleration measurements and compares the acceleration measurements to a value range to determine if the wearer is currently experiencing a fall event. The processor (108, 208) generates a signal in response to the detection of a fall event and the transmitter (110, 210) transmits the signal to a remote signal receiver (104, 204).

Abstract: A method and apparatus non-intrusive tracing. The method includes: counting selected events by multiple counters; sampling the multiple counters to retrieve multiple counter values in response to predefined triggering events; receiving additional trace information that comprises at least one program counter value, and outputting, as a trace information, at least one of the multiple counters values and the additional trace information.

Abstract: A slot-based low Intermediate Frequency (‘IF’) radio receiver comprises an IF local oscillator for producing I and Q IF local oscillator signal components in phase quadrature, I and Q mixer channels for mixing the input signal with the I and Q IF local oscillator signal components to produce I and Q IF signal components. The IF local oscillator includes frequency alternation means for causing the IF local oscillator frequency to alternate a plurality of times during each frame between first and second values, one of which is greater and the other smaller than the desired carrier frequency of the input signal so as to reduce the effect of adjacent and alternate interferers. The phase of the baseband local oscillator is alternated in synchronism with the alternation of the IF local oscillator frequency.

Abstract: A scan cell and a method for detecting supply voltage degradation in an integrated circuit using the scan cell. The scan cell includes a voltage comparator and a scan flip-flop. The voltage comparator compares a supply voltage with a reference voltage to generate a comparator output signal. The scan flip-flop is coupled to the voltage comparator, and receives the comparator output signal. Use of the scan cell for detecting IR drop replaces expensive methods like FIB (Focused Ion Beam) and EBEAM (electron beam).

Abstract: A non-volatile memory system (230) includes a magnetoresistive random access memory (MRAM) (232) including a plurality of magnetoresistive memory cells, a floating-gate nonvolatile memory (234) including a plurality of floating-gate memory cells, and a controller (236) coupled to the MRAM (232) and to the floating-gate nonvolatile memory (234). The controller (236) is adapted to be coupled to a system bus (220) and controls a selected one of the MRAM (232) and the floating-gate nonvolatile memory (234) in response to an access initiated from the system bus (220).

Abstract: A programmable capacitor array does not require separate switching transistors because the capacitors themselves have a switchable capacitance, which capacitors are made in the manner of regular N channel transistors with their source/drains connected to each other. When a logic low is applied to the gate, the capacitance is relatively low and the capacitance is what is commonly called parasitic capacitance. The capacitance increases significantly when a logic high is applied to the gate because the logic high has the effect of inverting the channel. Thus, the capacitor array is made of transistors that themselves have switchable capacitance operated so that no separate switching transistors are required. This allows for construction of an array of unit capacitors to achieve monotonic operation and good linearity using conventional manufacturing of N channel transistors while achieving significant area savings and reduced power consumption.

Abstract: A continuous time sigma delta converter has a filter and converter components having known non-ideal characteristics. A compensation circuit has error modelling components arranged to model the non-ideal characteristics of the converter. A summation block combines a compensation signal from the compensation circuit with a non-ideal output signal from the converter in order to provide a compensated output signal. This has substantially no effect on other modulator performance characteristics and contributes to the implementation of giga sample-per-second Continuous Time sigma deltas having the dynamic range capabilities of traditional DT sigma deltas.

Abstract: A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200, 300, 400) that includes a semiconductor substrate (110, 210, 310, 410) having a first conductivity type and buried semiconductor region (115, 215, 315, 415) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120, 220, 320, 420) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130, 230, 330, 430) having the first conductivity type located above the first semiconductor region, a third semiconductor region (140, 240, 340, 440) having the second conductivity type located above the first semiconductor region, an emitter (150, 250, 350, 450) having the first conductivity type disposed in the third semiconductor region, and a collector (170, 270, 370, 470) having the first conductivity type disposed in the third semiconductor region.

Abstract: A method and system of testing an electronic device can be performed by estimating the die temperature using correlation data previously collected for other electronic devices. In one embodiment, correlation data can include (1) die temperatures measured and (2) currents drawn by the electronic devices, testing voltages for the electronic devices, or powers consumed by the electronic devices during the testing. The correlation data can be used to generate an equation or be stored in a table. A method of testing a subsequent electronic device can include testing the subsequent electronic device. The method can also include estimating a die temperature for the subsequent electronic device during testing, wherein the die temperature can be estimated at least in part using a current drawn by the subsequent electronic device, a testing voltage for the subsequent electronic device, or a power consumed by the subsequent electronic device.

Abstract: An electronic device including a multi-gate electrode structure overlying the channel region further comprising a first and second gate electrode spaced apart from each other by a layer, and a process for forming the electronic device is disclosed. The multi-gate electrode structure can have a sidewall spacer structure having first and second portions. The first and second gate electrodes can have different conductivity types. The electronic device can also include a first gate electrode of a first conductivity type overlying the channel region, a second gate electrode of a second conductivity type lying between the first gate electrode and the channel region, and a first layer capable of storing charge lying between the first gate electrode and the substrate.

Abstract: An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance.

Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

Abstract: An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.

Abstract: A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

Abstract: A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.

Abstract: A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.

Abstract: A communication system having an echo canceller is disclosed. One embodiment of the echo canceller includes an adaptive filter used to provide an estimate of reflected echo which is removed from the send signal. The echo canceller may also include a near-end talker signal detector which may be used to prevent the adaptive filter from adapting when a near-end talker signal is present. The echo canceller may also include a nonlinear processor used to further reduce any residual echo and to preserve background noise. The echo canceller may also include a monitor and control unit which may be used to monitor the filter coefficients and gain of the adaptive filter to maintain stability of the echo canceller, estimate pure delay, detect a tone, and inject a training signal. The echo canceller may also include a nonadaptive filter used to reduce the length of the adaptive filter.

Abstract: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.