Patents Assigned to Fuji Electric Device
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Publication number: 20090219006Abstract: An electric power converter facilitates performing soft switching in the two-way electric-power-conversion operation thereof, and reducing the manufacturing costs thereof and the losses caused therein, The electric power converter includes a first switching device; a second switching device; a first series circuit including capacitor, a diode, the primary winding of transformer, and a third switching device; a second series circuit including a capacitor, a fourth switching device, the primary winding of transformer, and a diode; a third series circuit including a diode and the secondary winding of transformer; and a voltage clamping element connected in parallel to the primary winding of transformer. The first series circuit is connected in parallel to the first switching device, and the second series circuit is connected in parallel to second switching device. The third series circuit is connected between the DC output terminals.Type: ApplicationFiled: February 20, 2009Publication date: September 3, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Masakazu Gekinozu
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Publication number: 20090218643Abstract: An object of the present invention is to solve problems in that aluminum electrodes, aluminum wires, and I/O terminals are corroded by corrosive gasses when a pressure of a pressure medium containing corrosive matters such as exhaust gas is measured with a semiconductor sensor; and improve not only the corrosion resistance of the sensor chip but also the corrosion resistance of the portion particularly functioning as the pressure receiver. Each of the aluminum electrodes that is likely to be corroded portions is prevented from being corroded by forming a titanium-tungsten layer and gold layer on the aluminum electrode. The connecting wires are prevented from being corroded by corrosive matters by using gold wires. The I/O terminals are also prevented from being corroded by applying gold plating.Type: ApplicationFiled: November 1, 2005Publication date: September 3, 2009Applicants: Hitach, Ltd., Fuji Electric Device Technology Co., Ltd.Inventors: Toshiaki Kaminaga, Masahide Hayashi, Katusmichi Ueyanagi, Kazunori Saito, Mutsuo Nishikawa
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Publication number: 20090218313Abstract: There is provided a method for manufacturing a patterned magnetic recording medium including a step of completely removing an etching resist on a magnetic layer 3, which is used for etching the magnetic layer 3, without deteriorating magnetic characteristics of the magnetic layer 3. The step of removing the etching resist used for etching the magnetic layer 3 includes the steps of irradiating the etching resist on the magnetic layer 3 or the first protective layer 4 with an excimer VUV laser under a reduced pressure and immersing the resist coating 5 remaining on the magnetic layer 3 or the first protective layer 4 into a resist removing agent solution to wash off the resist coating 5.Type: ApplicationFiled: February 27, 2009Publication date: September 3, 2009Applicants: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD., WASEDA UNIVERSITYInventors: Satomi Kajiwara, Shuichi Shoji, Jun Mizuno, Hidetoshi Shinohara
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Patent number: 7582193Abstract: A method for producing a magnetic recording medium in which the noise of the magnetic recording medium is reduced and the thermal stability of the recorded magnetization is improved, while enabling easy writing to be carried out by a recording head, is disclosed. The magnetic recording medium of the present invention includes an underlayer having an hcp crystal structure and a magnetic layer produced by a multilayer lamination of Co/Pt or the like. The deposition rate of the underlayer is equal to or lower than 0.7 nm/second. The magnetic layer contains added silicon oxide at 1 to 10 mol %. The present method includes a step for subjecting the surface of the underlayer to Ar gas mixed with oxygen of a mass/flow rate ratio of 1% to 10% under a gas pressure of 0.1 to 10 Pa for 1 to 10 second(s). The magnetic recording medium may include an orientation control layer and a soft magnetic backing layer. Ku, Ku1, and Ku2 are controlled to provide both of thermal stability and easy writing.Type: GrantFiled: April 11, 2005Date of Patent: September 1, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventor: Yasuyuki Kawada
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Publication number: 20090212373Abstract: A semiconductor device facilitates securing a high breakdown voltage and reducing a chip area thereof includes a low-potential gate driver circuit disposed on a semiconductor substrate, a high-breakdown-voltage junction edge-termination structure disposed in a peripheral portion of a high-potential gate driver circuit, disposed on the semiconductor substrate, for separating the low-potential gate driver circuit and the high-potential gate driver circuit from each other. A trench is disposed in the edge termination structure and between an n+-type source layer and an n+-type drain layer in a level shift circuit in the high-potential gate driver circuit, and an oxide film fills the trench to form a dielectric region in trench.Type: ApplicationFiled: February 26, 2009Publication date: August 27, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Taichi KARINO, Akio KITAMURA
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Publication number: 20090208778Abstract: A patterned magnetic recording medium includes a magnetic layer having a track-shape and/or dot-shape relief pattern which demarcates information recording regions; a first protective layer covering the magnetic layer; and a second protective layer formed on the first protective layer and including a tetrahedral carbon (ta-C) film. The first protective layer has excellent corrosion resistance and the second protective layer has excellent magnetic head sliding characteristics. A method for manufacturing the medium includes forming an etching pattern of photohardening etching resist on an underlayer or magnetic layer using an imprinting method and etching the underlayer or magnetic layer to form a relief pattern; forming the first protective layer on the relief pattern of the magnetic layer using plasma CVD; and forming the second protective layer including a tetrahedral carbon (ta-C) film, on at least respective top portions of the relief pattern, by a FCA method or by a FCVA method.Type: ApplicationFiled: February 10, 2009Publication date: August 20, 2009Applicant: Fuji Electric Device Technology Co., Ltd.Inventor: Michiko Horiguchi
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Patent number: 7574919Abstract: An integrated sensor includes a pressure sensor integrated with a temperature sensor. When the sensor is attached to an object of attachment at a mounting position at an angle of ?rq degrees with respect to an ideal attachment position, in which a central axis of at sensor body element of the temperature sensor element is disposed perpendicular to a direction in which a gas to be measured passes through the object of attachment, an inclination angle ?pos at which the central axis of the sensor body element is inclined at the mounting position with respect to a position of the central axis of the main body element at the ideal attachment position is set according to the following equation: (?rq??allow)??pos?(?rq+?allow) wherein ?allow represents an allowable angle at which an allowable response speed of the temperature sensor element is obtained.Type: GrantFiled: November 9, 2007Date of Patent: August 18, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Kazunori Saito, Kimihiro Ashino, Katsumichi Ueyanagi
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Patent number: 7571652Abstract: A pressure sensor apparatus and a pressure sensor housing are provided that are capable of preventing the occurrence of frozen moisture, swelling of a gel-like coating member and damage of a pressure sensor element without accumulating moisture, oil, gasoline or the like on a protective wall even when the pressure sensor apparatus is disposed obliquely. The protective wall prevents entry of foreign matter into the pressure detection chamber, or a pressure sensor housing of the pressure sensor apparatus. The protective wall has an inclined surface that is provided with an angle ?8a in which a second angle ?2 is acquired between a horizontal line HL and the inclined surface that slopes downward when the pressure sensor apparatus is disposed obliquely by a first angle ?1 with respect to the horizontal line HL.Type: GrantFiled: November 13, 2007Date of Patent: August 11, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Kazunori Saito, Kimihiro Ashino, Katsumichi Ueyanagi
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Patent number: 7572683Abstract: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n?-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.Type: GrantFiled: November 9, 2006Date of Patent: August 11, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Manabu Takei, Tatsuya Naito, Michio Nemoto
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Publication number: 20090194785Abstract: A p-type body region and an n-type buffer region are formed on an n? drift region. An n++ emitter region and a p++ contact region are formed on the p-type body region in contact with each other. A p++ collector region is formed on the n-type buffer region. An insulating film is formed on the n? drift region, and a gate insulating film is formed on the n++ emitter region, the p-type body region, and the n drift region. A gate electrode is formed on the insulating film and the gate insulating film. A p+ low-resistivity region is formed in the p-type body region and surrounding the interface between the n++ emitter region and between the p-type body region and the p++ contact region. The p-type body region has two local maxima of an impurity concentration profile at the interface between the body region and the gate insulating film.Type: ApplicationFiled: January 9, 2009Publication date: August 6, 2009Applicant: Fuji Electric Device Technology Co., Ltd.Inventors: Hong-Fei Lu, Mizushima Tomonori
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Publication number: 20090194786Abstract: A semiconductor device includes deep first field limiting rings, shallow second field limiting rings, insulation films covering each surface portion of each of the first and the second field limiting rings, and conductive field plates each in contact with a surface of each of the first and the second field limiting rings. Each of the field plates project over a surface of each of the insulation films between the first field limiting rings and the second field limiting rings.Type: ApplicationFiled: February 3, 2009Publication date: August 6, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Susumu IWAMOTO, Takashi KOBAYASHI
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Publication number: 20090189181Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.Type: ApplicationFiled: January 27, 2009Publication date: July 30, 2009Applicants: DENSO CORPORATION, Fuji Electric Device Technology Co., Ltd.Inventors: Masaki Koyama, Yoshifumi Okabe, Makoto Asai, Takeshi Fujii, Koh Yoshikawa
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Publication number: 20090189580Abstract: A drive control apparatus controls a drive of an inductive load having a current flowing therethrough. The drive control apparatus includes a drive control device for controlling a variation of the current flowing through the inductive load within a certain period by Pulse Width Modulation control so as to come close to a reference current value, and a reference value control device for controlling a fluctuation period of the reference current value and making the fluctuation period of the reference current value longer than that of the current flowing through the inductive load by the Pulse Width Modulation control.Type: ApplicationFiled: January 21, 2009Publication date: July 30, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO.,LTD.Inventors: Masashi AKAHANE, Motomitsu IWAMOTO, Haruhiko NISHIO, Minoru NISHIO, Hiroshi TOBISAKA
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Publication number: 20090184340Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.Type: ApplicationFiled: January 22, 2009Publication date: July 23, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Michio NEMOTO, Haruo NAKAZAWA
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Publication number: 20090184698Abstract: A switching power supply exhibits high conversion efficiency and facilitates reducing the size thereof. The switching power supply includes a half-bridge circuit including a first series circuit formed of switching devices Q1 and Q2 and connected between the output terminals of a DC power supply; and a second series circuit connecting primary inductance Lr1 of transformer T1, primary inductance Lr2 of transformer T2 and capacitor Cr in series. The second series circuit is connected between the output terminals of the half-bridge circuit, and is made to conduct a series resonance operation. The switching devices Q1 and Q2 is controlled at the ON-duties of 0.5 for reducing the breakdown voltages of rectifying diodes D1 and D2 on the secondary side of transformers T1 and T2 and for improving the conversion efficiency of the switching device.Type: ApplicationFiled: January 13, 2009Publication date: July 23, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Yukihiro Nishikawa
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Publication number: 20090181264Abstract: A method for manufacturing a patterned magnetic recording medium that allows processing only required sites with high precision, in a dry etching process during formation of an uneven pattern in an interlayer. The method includes forming sequentially, on a substrate, a soft magnetic layer, an etching stop layer, a seed layer, an interlayer, a hard mask layer and a resist; obtaining a resist pattern by patterning the resist; obtaining a patterned hard mask layer by etching the hard mask layer using the resist pattern as a mask; stripping the resist pattern; obtaining a patterned interlayer by etching the interlayer using the patterned hard mask layer as a mask; stripping the patterned hard mask layer; and forming a magnetic recording layer by forming a perpendicular orientation section on the patterned interlayer, and forming a random orientation section on the seed layer.Type: ApplicationFiled: January 12, 2009Publication date: July 16, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Katsumi TANIGUCHI
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Publication number: 20090174076Abstract: A semiconductor device includes a semiconductor substrate; a metal electrode wiring laminate on the semiconductor substrate, the metal electrode wiring laminate being patterned with a predetermined wiring pattern; the metal electrode wiring laminate including an undercoating barrier metal laminate and aluminum or aluminum alloy film on the undercoating barrier metal laminate; and organic passivation film covering the metal electrode wiring laminate, wherein the barrier metal laminate is a three-layered laminate including titanium films sandwiching a titanium nitride film. The semiconductor device according to the invention facilitates improving the moisture resistance of the portion of the barrier metal laminate exposed temporarily in the manufacturing process, facilitates employing only one passivation film, facilitates preventing the failures caused by cracks from occurring and the failures caused by Si nodules remaining in the aluminum alloy from increasing.Type: ApplicationFiled: October 1, 2008Publication date: July 9, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Koji SASAKI, Kazuo MATSUZAKI, Takashi KOBAYASHI
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Patent number: 7557007Abstract: The method for manufacturing a semiconductor device according to the invention includes forming a thick silicon oxide film uniformly in a trench. Argon ions or the like implanted obliquely into the trench to form an ion implanted damaged region selectively in the portion of the silicon oxide film on the trench sidewall utilizing the shadowing effects of the oblique ion implantation. The silicon oxide film is wet etched to selectively remove the silicon oxide film in the ion implanted damaged region utilizing the etching rate difference, wherein the etching rate is faster in the damaged region than in the undamaged region. As a result, a thick residual oxide film is formed on the bottom and the lower sidewall portion of the trenchwithout causing any bird's beak.Type: GrantFiled: December 30, 2005Date of Patent: July 7, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Kazuo Shimoyama, Mutsumi Kitamura, Hongfei Lu
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Publication number: 20090153227Abstract: A temperature sensor circuit is provided that facilitates preventing a too-high overshooting voltage from occurring at an output terminal when a power supply is connected to the temperature sensor circuit. The temperature sensor circuit includes a short-circuiting device, disposed in parallel to depletion mode NMOS, that short-circuits the drain and source of depletion mode NMOS when a power supply is connected; and delay device that transmits a signal for short-circuiting the drain and source of depletion mode NMOS for a certain period from the time point of power supply connection to short-circuiting device for preventing the voltage at output terminal of temperature sensor circuit from overshooting.Type: ApplicationFiled: December 15, 2008Publication date: June 18, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Takatoshi OOE, Ryuu SAITOU, Morio IWAMIZU
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Publication number: 20090148723Abstract: A substrate for a recording medium suited for thermally assisted recording methods has a disc shape with a center hole and includes a silicon single-crystal supporting member; an SiO2 film formed on the silicon single-crystal supporting member; a main face having a film thickness of the SiO2 film thereon which is less than 10 nm; a substrate inner periphery end face adjacent to the center hole; a substrate inner periphery chamfer portion adjacent to the main face and to the substrate inner periphery end face; a substrate outer periphery end face positioned on the side of the main face opposite the substrate inner periphery end face; and a substrate outer periphery chamfer portion adjacent to the main face and to the substrate outer periphery end face. A magnetic recording medium includes at least the above substrate and a magnetic recording layer formed on the substrate.Type: ApplicationFiled: December 8, 2008Publication date: June 11, 2009Applicant: Fuji Electric Device Technology Co., Ltd.Inventor: Kouichi TSUDA