Patents Assigned to Fuji Electric Device
  • Patent number: 7626856
    Abstract: A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic fine wire and current electrodes to measure voltage across part of the ferromagnetic fine wire in cooperation with the current electrodes. A magnetic domain wall is induced in the ferromagnetic fine wire when the element is manufactured. A depression is formed in the surface on top of the ferromagnetic fine wire between the voltage electrodes, and between one of the current electrodes and one of the voltage electrodes. Voltage is measured between the two voltage electrodes when reading current is applied, to determine whether the magnetic domain wall is present between the two voltage electrodes, whereby recorded data can be identified.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: December 1, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Takuya Ono
  • Publication number: 20090291326
    Abstract: A protective film is disclosed that is mainly composed of a tetrahedral amorphous carbon (ta-C film) that is denser than a DLC film formed by a plasma CVD method and containing aggregate particles so reduced as to a necessary and sufficient level, to provide a method of manufacturing such a protective film, and to provide a magnetic recording medium comprising such a protective film. The film is mainly composed of a ta-C film formed by a filtered cathodic arc method using a cathode target of glass state carbon. A magnetic recording medium is disclosed which includes a substrate, a magnetic recording layer, and the protective film mainly composed of a ta-C film.
    Type: Application
    Filed: May 22, 2009
    Publication date: November 26, 2009
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventor: Naruhisa NAGATA
  • Publication number: 20090289344
    Abstract: A semiconductor device includes an insulating substrate; at least one semiconductor element mounted on a first principal surface of the insulating substrate; and a heat radiator joined through a solder member to a second principal surface of the insulating substrate opposite to the first principal surface on which the semiconductor element is mounted. The solder member contains at least tin and antimony, and the antimony content of the solder member is in a range of from 7% by weight to 15% by weight, both inclusively. Thus, reliability of the semiconductor device is improved.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 26, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Akira Morozumi
  • Publication number: 20090291234
    Abstract: A method for depositing a thin film for a magnetic recording medium includes the steps of placing a substrate for a recording medium having a magnetic recording layer thereon on a substrate holder rotatably arranged within a film deposition chamber; and supplying a plasma beam from a plasma beam formation portion to the film deposition chamber so as to form a thin film of ta-C on the magnetic recording layer. In supplying the plasma beam, an inclination angle formed by a normal line to a surface of the magnetic recording layer and a plane orthogonal to a direction of incidence of the plasma beam is changed from a minimum inclination angle to a maximum inclination angle according to an increase in film thickness of the ta-C thin film.
    Type: Application
    Filed: May 18, 2009
    Publication date: November 26, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Katsunori Suzuki, Takeshi Watanabe
  • Publication number: 20090289670
    Abstract: A buffer circuit is provided between a gate terminal of a pull-down transistor and a threshold circuit receiving a gate signal as an input signal. A voltage applied to an output terminal of a power semiconductor element from an external battery power supply is supplied to the buffer circuit through a resistive element. The buffer circuit converts the level of an on-signal output from the threshold circuit into a voltage higher than the threshold of the pull-down transistor, so that the pull-down transistor operates surely to turn off the power semiconductor element even when the level of the gate signal is low. Thus, there is provided a semiconductor integrated circuit device having a power semiconductor element which can be turned off by sure operation of a pull-down semiconductor element.
    Type: Application
    Filed: May 26, 2009
    Publication date: November 26, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Yoshiaki TOYODA, Kenichi ISHII, Morio IWAMIZU
  • Publication number: 20090291520
    Abstract: A manufacturing method is provided for manufacturing a semiconductor apparatus including a main semiconductor device and a subsidiary semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs.
    Type: Application
    Filed: May 22, 2009
    Publication date: November 26, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Koh YOSHIKAWA
  • Patent number: 7622887
    Abstract: Power electronics equipment includes air-cored insulating transformers inserted between a control circuit grounded to a vehicle body and an upper arm biased at a high voltage, and air-cored insulating transformers between the control circuit grounded to the vehicle body and the lower arm biased at a high voltage. Each of the air-cored insulating transformers includes a primary winding and a secondary facing to each other. The power electronics equipment facilitates improving resistance against hazardous environments, suppressing the deterioration by aging, reducing the adverse effects of noise caused by external magnetic flux, and transmitting and receiving signals while insulating the low and high voltage sides electrically from each other.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: November 24, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Hiroyuki Yoshimura
  • Patent number: 7622205
    Abstract: A disk substrate for a perpendicular magnetic recording medium is, disclosed. The substrate exhibits sufficient productivity, serves the function of a soft magnetic backing layer of the perpendicular magnetic recording medium, and scarcely generates noise. A perpendicular magnetic recording medium using such a substrate also is disclosed. The disk substrate comprises at least a soft magnetic underlayer formed on a nonmagnetic base plate by means of an electroless plating method. The thermal expansion coefficient of the soft magnetic underlayer is larger than a thermal expansion coefficient of the nonmagnetic disk-shaped base plate. A saturation magnetostriction constant ?s satisfies a relation ?s??1×10?5.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: November 24, 2009
    Assignee: Fuji Electric Device Technology Co. Ltd.
    Inventors: Hiroyuki Uwazumi, Youichi Tei, Kengo Kainuma, Kazuhito Higuchi, Akira Iso, Hajime Kurihara
  • Publication number: 20090284991
    Abstract: A switching power supply includes a control circuit controlling ON and OFF of switching devices Q1 and Q2 and having an error amplifying circuit that controls a DC output voltage at a constant preset value, an oscillator circuit that controls the switching frequency in response to the output signal level FB of an error amplifying circuit, and a pulse width control circuit PWM that controls the pulse width in response to the output signal such that the ON-periods of switching devices Q1 and Q2 are equal to each other. The ON and OFF of switching devices Q1 and Q2 is controlled based on the output from oscillator circuit VCO when the output signal is higher than a threshold level. The switching frequency is fixed when the output signal level FB is lower than the threshold level.
    Type: Application
    Filed: May 1, 2009
    Publication date: November 19, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Yukihiro Nishikawa
  • Publication number: 20090283776
    Abstract: A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and a second trench in a source electrode part (Schottky diode part) are disposed so that the first and second trenches are close to each other while and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a wide band gap semiconductor device which is small in size and low in on-resistance and loss, and in which electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage to thereby increase avalanche breakdown tolerance at turning-off time.
    Type: Application
    Filed: April 17, 2009
    Publication date: November 19, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Noriyuki Iwamuro
  • Publication number: 20090284200
    Abstract: In an AC motor driving circuit, a current source rectifier is provided on the output side of an AC generator and an AC motor is connected to the output side of the current source rectifier through a voltage source inverter. Along with this, one of terminals of each of a plurality of bidirectional switches is connected to its corresponding output terminal of the voltage source inverter, the other terminals of a plurality of the bidirectional switches are lumped together to be connected to one of terminals of a storage battery, and the other terminal of the storage battery is connected to one of DC input terminals of the voltage source inverter. This eliminates need for a large capacitor at a DC link and a reactor in a chopper which were previously necessary, by which the AC motor driving circuit is downsized.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 19, 2009
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventors: Michio Iwahori, Masakazu Gekinozu
  • Publication number: 20090286093
    Abstract: According to one embodiment of the invention, there is provided a lead-free solder including an alloy rolled into a shape of sheet. The alloy includes: tin; from 10 wt % to less than 25 wt % of silver; and from 3 wt % to 5 wt % of copper. The alloy is free from lead.
    Type: Application
    Filed: July 2, 2009
    Publication date: November 19, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Kazuyuki MAKITA, Masaki Ichinose, Taketo Watashima, Masayuki Soutome, Mitsuo Yamashita, Takeshi Asagi, Masatoshi Hirai, Toru Murata
  • Publication number: 20090280646
    Abstract: A micro-transformer manufacturing method is provided, which can improve throughput, prevent a crack from entering an insulating film between coils, and manufacture the micro-transformer without using a mask material having a high selection ratio. An insulating film is deposited on the whole face of a semiconductor substrate having an impurity-diffused region. This insulating film is partially removed to form a first opening and a second opening. A primary coil is formed such that a center pad contacts the impurity-diffused region through the first opening. A thin insulating film is deposited on the primary coil. An insulator material having a secondary coil formed thereon is adhered onto the insulating film on the primary coil by adhesive tape. The insulator material is sized to not cover both a pad, connected with the center pad of the primary coil through the impurity-diffused region, and an outer-end pad of the primary coil.
    Type: Application
    Filed: April 24, 2008
    Publication date: November 12, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Masanobu IWAYA, Reiko HIRUTA, Katsunori UENO, Kunio MOCHIZUKI
  • Patent number: 7615984
    Abstract: A DC-DC converter can prevent intermittent failure of a PWM or driving signal (VM) when a load becomes light and prevent generation of unusual noise from a transformer. The converter includes a transformer (2) having a primary winding (2a) and a secondary winding (2b), a semiconductor switching element (17) connected to the primary winding (2a), and a control unit controlling turning-ON and OFF periods of the switching element (17) so that an output voltage (VO) matches a reference value (VREF). By controlling the turning ON and OFF operation of the switching element (17), a DC voltage exactly equal to the reference value (VREF) can be supplied to a load (5).
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: November 10, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Kesanobu Kuwabara
  • Publication number: 20090272982
    Abstract: A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench 10p. In this manner, there is provided a trench gate type semiconductor device and a method of producing the same, in which: the cell pitch can be reduced even when a wide band gap semiconductor is used as a main semiconductor substrate; good ohmic contacts can be obtained; and an excessive electric field is prevented from being applied to an insulating film in the bottom of each trench.
    Type: Application
    Filed: March 3, 2009
    Publication date: November 5, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Shun-ichi NAKAMURA, Yasuyuki KAWADA
  • Publication number: 20090273325
    Abstract: A current negative-feedback circuit comprises a current detection unit and a sawtooth-shaped waveform generation unit. The current detection unit comprises a first P-ch MOSFET Q2 and a second P-ch MOSFET Q3 which constitute a current mirror circuit, a current adjustment resistor R4, a current detection resistor R1, and a constant current source I1. The current mirror circuit outputs current almost proportional to the charge current of an inductance via a switching device or outputs a current which is the quadratic function of the charge current of an inductance. The sawtooth-shaped waveform generation means adds the constant charge current of the constant current source I2 and the current output from the current mirror circuit, charges the capacitor C1, and generates a sawtooth-shaped waveform.
    Type: Application
    Filed: February 13, 2009
    Publication date: November 5, 2009
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventors: Yasunori Nakahashi, Satoshi Yamane
  • Publication number: 20090268488
    Abstract: A semiconductor device controls a switching power supply. The semiconductor device includes a current inflow terminal; a starter circuit to cause a starting current to flow from the current inflow terminal to a power supply terminal to charge a capacitor externally connected to the power supply terminal; a control unit which controls the starter circuit to turn on to charge the capacitor with the starting current and controls the starter circuit to turn off to perform brown-out detection; a comparator which detects a brown-out state while the starter circuit is turned off; and a brown-out detection unit which receives output signals from the comparator and the control unit as inputs. The brown-out detection is performed while the starter circuit is off, so that the current inflow terminal for the starter circuit is used in common as a voltage detection terminal for detection of the brown-out state.
    Type: Application
    Filed: April 10, 2009
    Publication date: October 29, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Masanari Fujii
  • Publication number: 20090261514
    Abstract: An imprinting method forms a predetermined pattern in a resist surface of a substrate coated with a photo-curing type resist by using a mold having a pattern of projections and recesses formed in a transfer surface. The method includes an alignment step, a press step, a UV irradiation step, and a release step. The steps are performed in plural units selected from independent units, composite units, and combinations of independent units and composite units. The mold and the substrate are paired with each other and conveyed between the units. An imprinting apparatus includes plural units which perform the steps in the imprinting method and which are selected from independent units in each of which one step is executed, composite units in each of which plural of steps are executed, and combinations of independent units and composite units; and conveying devices which convey the mold and the substrate.
    Type: Application
    Filed: April 22, 2009
    Publication date: October 22, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Shinji UCHIDA
  • Publication number: 20090261504
    Abstract: An imprinting method includes the steps of setting a room-temperature imprint resist-coated substrate and a mold having a transfer surface having a pattern of projections and recesses therein in an assembling jig, pressing the patterned surface of the mold against the resist surface of the substrate, and releasing the mold from the substrate to separate the substrate, the mold and the assembling jig from one another. The steps are performed in plural independent units in each of which one step is executed, and the mold and the substrate are paired with each other by the assembling jig and conveyed between the units in a range of from the alignment step to the separation step. An imprinting apparatus includes an alignment unit which performs the alignment step, a press unit performing the press step, and a separation unit performing the separation step, wherein conveyance devices are provided to convey the mold and substrate between units.
    Type: Application
    Filed: April 22, 2009
    Publication date: October 22, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Shinji UCHIDA
  • Patent number: 7606082
    Abstract: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: October 20, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Hiroshi Shimabukuro, Hideto Kobayashi, Yoshihiro Shigeta, Gen Tada