Patents Assigned to Fuji Electric Device
  • Patent number: 7723000
    Abstract: An electrophotographic photoconductor includes an undercoat layer and a photosensitive layer sequentially provided on a conductive substrate. The undercoat layer is mainly composed of a resin and contains a metal oxide. The resin is provided by mixing and polymerizing raw materials of aromatic dicarboxylic acid in a range of 0.1 to 10 mol %, two or more types of dicarboxylic acid other than the aromatic dicarboxylic acid, two or more types of diamine, and at least one type of cyclic amide compound. The resin exhibits an acid value and a base value each of at most 6.0 KOH mg/g. Advantageously, generation of secondary aggregates in the undercoat layer, which result in image defects such as black spots and fogging on a white field, is suppressed.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: May 25, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Shinjirou Suzuki, Yoichi Nakamura, Ikuo Takaki, Kazuki Nebashi
  • Patent number: 7723817
    Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface. This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
    Type: Grant
    Filed: May 29, 2006
    Date of Patent: May 25, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Hiroshi Kanemaru, Naoki Kumagai, Yuichi Harada, Yoshihiro Ikura, Yoshiaki Minoya
  • Patent number: 7723846
    Abstract: A power semiconductor module and a method of manufacture thereof includes a lead frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: May 25, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Osamu Ikawa, Eiji Mochizuki, Masayuki Soutome, Norio Arikawa
  • Patent number: 7719859
    Abstract: A switching power supply device has a drive circuit that can minimize a loss while being compact. The drive circuit turns on and off a high-side switching element (MOSFET) according to a positive or negative voltage developed at a tertiary winding of a transformer. The drive circuit includes a control unit that detects the development time, during which the negative voltage is developed at the tertiary winding, as the on time of a low-side switching element, and makes the on time of the high-side switching element nearly or substantially equal to the development time.
    Type: Grant
    Filed: November 4, 2007
    Date of Patent: May 18, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Yukihiro Nishikawa
  • Patent number: 7719092
    Abstract: The power semiconductor module includes a module package housing power semiconductor devices therein and a magnetic core set around the module package, such that magnetic core surrounds the power semiconductor devices such as IGBTs. Alternatively, the magnetic core is built in the module package such that the outer circumference faces of magnetic core and the side faces of module package form side faces of the power semiconductor module. The power semiconductor module according to the invention facilitates replacing the magnetic core, setting the magnetic core around the module package thereof, reducing the size thereof, simplifying the structure thereof, and easy manufacture thereof.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: May 18, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Hiromu Takubo
  • Publication number: 20100118456
    Abstract: A CMOS IC according to the invention includes a discharging circuit for preventing electrostatic breakdown from occurring. The discharging circuit includes a discharging NMOSFET Qe, which couples a gate terminal node Vgp continuous to the gate of an outputting PDMOS transistor Qo and the gate of a discharging NMOSFET Qe via a capacitor Ce, and connects the drain of the discharging NMOSFET Qe to a gate terminal node Vgp continuous to the gate terminal of the outputting PDMOS transistor Qo. The discharging circuit 300 also includes a pull-down resistor disposed between the gate of the discharging NMOSFET Qe and the ground for preventing the discharging NMOSFET Qe from operating in a steady state condition. The CMOS IC according to the invention makes the discharging NMOSFET Qe trigger to operate by the potential change at the node corresponding to the potential change of the power supply line, when a surge caused by static electricity and such is applied to the power supply line.
    Type: Application
    Filed: September 14, 2009
    Publication date: May 13, 2010
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Masayuki YAMADAYA
  • Publication number: 20100119876
    Abstract: A magnetic recording medium includes a substrate, and a soft magnetic layer, a crystal orientation control layer, a magnetic recording layer, and a protective layer formed sequentially on the substrate. The magnetic recording layer includes at least one granular magnetic layer having a granular structure and a non-granular magnetic layer having a non-granular structure. The at least one granular magnetic layers includes a plurality of magnetic portions and a separation portion surrounding the magnetic portions. The separation portion has magnetic characteristics different from the magnetic characteristics of the magnetic portions. The non-granular magnetic layer is a continuous film.
    Type: Application
    Filed: November 6, 2009
    Publication date: May 13, 2010
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventor: Shinji Uchida
  • Patent number: 7714363
    Abstract: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: May 11, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Takahiro Nomiyama, Gen Tada, Yoshihiro Shigeta
  • Patent number: 7714353
    Abstract: A trench-type insulated-gate semiconductor device is disclosed that includes unit cells having a trench gate structure that are scattered uniformly throughout the active region of the device. The impurity concentration in the portion of a p-type base region, sandwiched between an n+-type emitter region and an n-type drift layer and in contact with a gate electrode formed in the trench via a gate insulator film, is the lowest in the portion thereof sandwiched between the bottom plane of n+-type emitter regions and the bottom plane of p-type base region and parallel to the major surface of a silicon substrate. The trench-type insulate-gate semiconductor device according to the invention minimizes the variation of the gate threshold voltage.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: May 11, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Yuichi Onozawa
  • Patent number: 7713794
    Abstract: A manufacturing method of a semiconductor device includes the steps of forming an insulating film having a prescribed repetition pattern on one surface of a semiconductor substrate and then depositing semiconductor layers on the one surface of the semiconductor substrate; forming trenches from the other surface of the semiconductor substrate in such a manner that the trenches come into contact with the semiconductor layer, that plural trenches are formed for each semiconductor chip to be formed on the semiconductor substrate, and that at least one pattern of the insulating film is exposed through the bottom of each trench; and covering the inside surfaces of the trenches and the other surface of the semiconductor substrate with a metal electrode.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: May 11, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Publication number: 20100110844
    Abstract: A master disk for batch transferring of predetermined information recorded therein to a magnetic recording medium includes a substrate transmitting laser light, and convex portions provided on the substrate and formed of material reflecting or blocking the laser light. The convex portions have a pattern corresponding to the predetermined information.
    Type: Application
    Filed: October 22, 2009
    Publication date: May 6, 2010
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Satomi Kajiwara
  • Publication number: 20100109647
    Abstract: In a semiconductor device, in particular a physical quantity sensing apparatus, the length and the width of the wiring connecting a sensor internal circuit and an output or power supply pad are adjusted so that the total parasitic resistance components R1 parasitic on the wiring and the sum Rf of the resistance values of resistors in the filter circuit for countermeasuring against electromagnetic noises satisfy the relational expression R1/RfĂ—100<25.
    Type: Application
    Filed: January 14, 2010
    Publication date: May 6, 2010
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Katsuyuki UEMATSU, Katsumichi UEYANAGI
  • Publication number: 20100109626
    Abstract: A power factor correction power supply unit for correcting a power factor includes a switching device, an input voltage detection circuit, an output voltage detection circuit, an error amplifier for outputting an error signal obtained by amplifying a difference between an output voltage detection signal and a reference voltage, an ON width generation circuit for generating an ON time width, an OFF width generation circuit for generating an OFF time width of the switching device, and a switching device driving circuit. The drive circuit conducts an ON/OFF control over the switching device upon receiving a turn-on timing signal for turning on the switching device as soon as the OFF time width is terminated and upon receiving a turn-off timing signal for turning off the switching device as soon as the ON time width is terminated.
    Type: Application
    Filed: August 31, 2009
    Publication date: May 6, 2010
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Jian Chen
  • Publication number: 20100109015
    Abstract: An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer.
    Type: Application
    Filed: September 4, 2009
    Publication date: May 6, 2010
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Katsunori UENO
  • Publication number: 20100112210
    Abstract: Spin coating method for a recording medium having a hole in the center, including moving a tip of a feeding nozzle to an initial position at a distance X above a recording surface and a distance A radially apart from a periphery of the hole, feeding a coating liquid onto the recording surface for a predetermined period of time while rotating the recording medium at a predetermined speed, and moving the tip from the initial position along a radial direction towards an outer periphery of the recording medium while keeping the tip above the recording surface at the distance X. X satisfies X?2 [3 r ?/(2 g C)]1/3, where ? and C respectively are surface tension and density of the coating liquid, r is the outer radius of the feeding nozzle, and g is the acceleration of gravity. A satisfies A?r+X/3.
    Type: Application
    Filed: November 6, 2009
    Publication date: May 6, 2010
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventor: Shinji Uchida
  • Publication number: 20100103550
    Abstract: A magnetic transfer device enables precise positioning of both disks while preventing generation of dust by sliding of a holder, and also secures a space for transfer magnet arrangement. A master disk on which is formed a magnetic signal pattern and a magnetic disk which is to receive transfer are accommodated and brought into close contact in opposition to each other within an interior space formed by a male-side holder which moves to approach and withdraw and a female-side holder. A plurality of positioning pins are brought into contact with the outer face of the male-side holder to position the male-side holder, and by installing the positioning pins at positions lower than both the master disk and the magnetic disk, dust generated by sliding of the positioning pins does not fall onto the face of the master disk or the magnetic disk.
    Type: Application
    Filed: October 21, 2009
    Publication date: April 29, 2010
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Narumi SATO
  • Publication number: 20100103559
    Abstract: A method of manufacturing a magnetic recording medium is disclosed, as well as a magnetic recording medium manufactured by the method. In the manufacturing method, the uneven pattern has magnetic recording elements in protruding portions formed above a substrate, and depressed portions between the recording elements are filled with a filling material. The method allows a high quality magnetic recording medium to be manufactured inexpensively by eliminating the process of removing excess filling material used to fill depressions between magnetic recording elements, because the method allows material to be filled only in the depressed portions of an uneven pattern. The method includes a technique rendering the wettability of the protruding portion surfaces and the depressed portion surfaces different prior to the process of filling with the filling material.
    Type: Application
    Filed: October 23, 2009
    Publication date: April 29, 2010
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Narumi SATO
  • Patent number: 7705443
    Abstract: An electrical connection inside a semiconductor device is established by lead frames formed of plural conductor plates. The lead frames are disposed three-dimensionally so that the respective weld parts thereof are exposed toward a laser light source used in the laser welding. The laser welding is then performed by irradiating a laser beam. According to the above, welding can be performed readily in a reliable manner. The productivity of the semiconductor device and the manufacturing method of the semiconductor device can be thus enhanced. In addition, because the lead frames have the cooling effect, they have the capability of a heat spreader. It is thus possible to provide a semiconductor device and a manufacturing method of the semiconductor device with high productivity.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: April 27, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Toshiyuki Yokomae, Katsumichi Ueyanagi, Eiji Mochizuki, Yoshinari Ikeda
  • Patent number: 7700971
    Abstract: An insulated gate silicon carbide semiconductor device is provided having small on-resistance. The device combines a static induction transistor structure with an insulated gate field effect transistor structure. The advantages of both the SIT structure and the insulated gate field effect transistor structure are obtained. The structures are formed on the same SiC semiconductor substrate, with the MOSFET structure above the SIT structure. The SIT structure includes a p+ gate region in an n-type drift layer on an n+ SiC semiconductor substrate, and an n+ first source region on the surface of the drift layer. The MOSFET structure includes a p-well region on the surface of the first source region, a second source region formed in the p-well region, and a MOS gate structure formed in a trench extending from the second source region to the first source region. The p+ gate region and a source electrode are conductively connected.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: April 20, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: RE41282
    Abstract: A perpendicular magnetic recording medium has a granular magnetic layer and a nonmagnetic underlayer of a metal or an alloy having a hexagonal close packed (hcp) crystal structure. A seed layer of a metal or an alloy of a face-centered cubic (fcc) crystal structure is provided under the nonmagnetic underlayer. Such a perpendicular magnetic recording medium exhibits excellent magnetic characteristics even when the thickness of the underlayer or the total thickness of the underlayer and the seed layer is very thin. Excellent magnetic characteristics can be obtained even when of the substrate is not preheated. Accordingly, a nonmagnetic substrate, such as a plastic resin can be employed to reduce the manufacturing cost.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: April 27, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Hiroyuki Uwazumi, Yasushi Sakai, Tadaaki Oikawa, Miyabi Nakamura