Patents Assigned to Fujitsu Limited
  • Patent number: 4425700
    Abstract: The method of manufacture of a semiconductor device having wirings or electrodes of silicide formed by: exposing parts of a single-crystal silicon layer formed on an insulating substrate, forming a film of metal over the exposed parts, and annealing so that a silicide is formed of the silicon and metal throughout the entire thickness of the silicon layer. The single-crystal silicon layer may be formed on a sapphire or spinel substrate having a film of silicon dioxide, sapphire or spinel, epitaxially grown on a silicon substrate.
    Type: Grant
    Filed: August 7, 1981
    Date of Patent: January 17, 1984
    Assignee: Fujitsu Limited
    Inventors: Nobuo Sasaki, Motoo Nakano
  • Patent number: 4426686
    Abstract: A read-only memory device in which the presence or absence of a MOS transistor in a memory cell located at each intersection between word lines and bit lines is disclosed. In this device, when data belonging to one word line is written into the memory cells, the original data or the inverted data of the original data is written. The determination whether or not the data is inverted is performed in accordance with the number of data "0" or "1" belonging to each word line.
    Type: Grant
    Filed: May 8, 1981
    Date of Patent: January 17, 1984
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Yamamoto, Hitoshi Takahashi
  • Patent number: 4426595
    Abstract: An acoustic surface wave device comprises a piezoelectric substrate (1), an input transducer (2), an output transducer (3) and acoustical absorbent layer patterns (5, 6) for absorbing undesired acoustic surface waves and bulk waves (S.sub.4, S.sub.5). Each of the acoustical absorbent layer patterns (5, 6) has zigzag-shaped or triangular shaped edges, i.e., a recess portion (R.sub.1, R.sub.3) and a protruding portion (R.sub.2, R.sub.4). The recess portion has a further recess portion (R.sub.1 ', R.sub.3 ') which is formed diagonally with respect to the propagation path of acoustic surface waves.
    Type: Grant
    Filed: January 22, 1982
    Date of Patent: January 17, 1984
    Assignee: Fujitsu Limited
    Inventors: Kuninori Kawaura, Sumio Yamada, Noboru Wakatsuki, Masaaki Ono, Shigeo Tanji, Yoshiro Fujiwara, Masanobu Yanagisawa
  • Patent number: 4426439
    Abstract: A negative photoresist emulsion, wherein after a film of negative photoresist emulsion on a substrate has been exposed for pattern writing in vacuum to charged particle beams or soft X-ray beams, the film-coated substrate is transferred to, and kept in, a chamber filled with non-oxidizing gas, and then the substrate is removed to the outside atmosphere. By this method, a curing effect of the photoresist film is prevented, enabling formation of fine patterns with precision. An apparatus for carrying out the above method, has a gas chamber filled with non-oxidizing gas connected to an exposure chamber, and the substrate, after such exposure, is kept in an atmosphere of non-oxidizing gas in the gas chamber before being removed to the outside atmosphere. In either the above-method or apparatus, the concentration of oxygen in the non-oxidizing gas must be less than 5%, preferably less than 1%.
    Type: Grant
    Filed: December 11, 1981
    Date of Patent: January 17, 1984
    Assignee: Fujitsu Limited
    Inventors: Koichi Kobayashi, Kenichi Kawashima, Shuzo Oshio
  • Patent number: 4426713
    Abstract: A synchronizing circuit provides a plurality of signal transmission paths having different delay times in the line for transmitting signals. A pilot signal circuit has a pilot signal generator circuit which operates on the sending side, and a pilot signal is sent via one of the paths having a different delay time to a plurality of latch circuits on the receiving side. The output of each of the latch circuits is compared by a predicting circuit, so as to predict the phase difference between the clock signals of sending clock system and the receiving clock system. According to the result of this prediction, the signal transmission path having the optimum delay time is selected, so as to transmit the received signal that has been synchronized to the latch on the receiving side.
    Type: Grant
    Filed: September 18, 1981
    Date of Patent: January 17, 1984
    Assignee: Fujitsu Limited
    Inventors: Kazuyuki Shimizu, Minoru Koshino
  • Patent number: 4425555
    Abstract: A dielectric filter module having an open housing which supports screws for adjusting the characteristics of the dielectric filter. The dielectric filter, which includes an elongated dielectric block having internal cavities and a conductive film extending from the exterior surface of the block into the internal cavities, is mounted in an openended metal housing which surrounds three sides of the dielectric filter. Suitable housings can be inexpensively fabricated to the necessary length from segments cut from commercially available channel members having C-shaped or I-shaped cross-sections. Wires extend through the open ends of the housing to connector elements on the surface of the block adjacent its ends. The connector elements can be adhesively secured metal members or locally deposited regions of metallic film. Either threaded holes on the housing or nut members mounted on the housing can be used for supporting the adjustment screws.
    Type: Grant
    Filed: October 23, 1981
    Date of Patent: January 10, 1984
    Assignee: Fujitsu Limited
    Inventors: Takeshi Meguro, Yukio Ito
  • Patent number: 4424525
    Abstract: A thin electron accumulation layer is generated along a heterojunction between two kinds of semiconductors each of which has a different electron affinity. This electron accumulation layer suffers less ionized-impurity scattering, because the thickness does not exceed the spread of an electron wave. A channel constituted with this electron accumulation enjoys an excellent electron mobility, particularly at cryogenic temperatures. A layer configuration fabricated with two different semiconductors having different electron mobilities and a similar crystal lattice coefficient, and including a single heterojunction, is effective to improve electron mobility. Such a layer configuration can be employed for production of an active semiconductor device with high electron mobility, resulting in high switching speed. The semiconductor devices including a FET, a CCD, etc., exhibit an excellent transfer conductance Gm.
    Type: Grant
    Filed: December 29, 1980
    Date of Patent: January 3, 1984
    Assignee: Fujitsu Limited
    Inventor: Takashi Mimura
  • Patent number: 4424588
    Abstract: Disclosed is a method of detecting the position of a symmetrical article by converting image signals of the article into binary information and detecting the position of the article based on the binary information. A first median point is determined, from the binary information, that is between two points of intersection between a first straight line intersecting the article and the sides of the article. A second median point is determined, from the binary information, that is between two points of intersection between a second straight line passing through the first median point, crossing the first straight line at right angles and crossing the sides of the article.
    Type: Grant
    Filed: August 26, 1981
    Date of Patent: January 3, 1984
    Assignee: Fujitsu Limited
    Inventors: Takashi Satoh, Isamu Shimada
  • Patent number: 4424582
    Abstract: A semiconductor memory device which writes information by rendering particular memory cells conductive or non-conductive, wherein, when a selected memory cell is to be read out, a power supply voltage is applied to the collector of a transistor which feeds a base current to a final stage transistor of a decoder circuit which is connected to word lines, and when information is to be written in, a voltage higher than the power supply voltage is applied to the same collector.
    Type: Grant
    Filed: April 21, 1980
    Date of Patent: January 3, 1984
    Assignee: Fujitsu Limited
    Inventors: Toshitaka Fukushima, Kazumi Koyama, Kouji Ueno, Tamio Miyamura, Yuichi Kawabata
  • Patent number: 4423492
    Abstract: A semiconductor EPROM device which comprises a plurality of floating gate type memory cell transistors and in which the threshold potential of the memory cell transistors is measured by changing the potential of a second power supply terminal to which is originally connected a high potential used for programming the EPROM device.
    Type: Grant
    Filed: December 11, 1981
    Date of Patent: December 27, 1983
    Assignee: Fujitsu Limited
    Inventor: Masanobu Yoshida
  • Patent number: 4423430
    Abstract: A superconductive logic device incorporating at least one Josephson junction comprises two superconductive electrodes, that is, a base electrode and a counter electrode with a thin insulating layer therebetween. The counter electrode has an extension for receiving an input signal and another extension connected to a ground plane. The input signal current which is supplied from the counter electrode to the ground plane acts on the Josephson junction with a magnetic field, while, a bias current is supplied from the base electrode and flows through the Josephson junction to the ground plane.
    Type: Grant
    Filed: February 20, 1981
    Date of Patent: December 27, 1983
    Assignee: Fujitsu Limited
    Inventors: Shinya Hasuo, Hideo Suzuki
  • Patent number: 4423431
    Abstract: A protective semiconductor integrated circuit device for protecting an internal circuit against an excessively high voltage has a first resistor of a low value resistance interposed between an input terminal and an input gate of the internal circuit. One of the drain and source regions of an MIS type transistor is connected to the input gate of the internal circuit to be protected and the other region of the source and drain is grounded. A capacitor is interposed between the gate of the MIS transistor and the input terminal. A second resistor or a diode of reverse polarity is interposed between the gate of the MIS transistor and ground. The protective device may be fabricated using, a bulk silicon, an insulating substrate such as sapphire, spinel or semi-insulating material, simultaneously with the internal circuit and without changing processes for fabrication of the internal circuit and without requiring any additional masking steps.
    Type: Grant
    Filed: December 24, 1980
    Date of Patent: December 27, 1983
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4423127
    Abstract: In the manufacture of a semiconductor device wherein a plurality of patterns are successively superimposed and printed on a semiconductor substrate, the invention offers a novel and useful method which includes (a) printing and forming on the semiconductor substrate a first pattern which includes a first alignment mark, (b) in forming a second pattern on the substrate, positioning and printing a second alignment mark contained in a second pattern relative to the first alignment mark on the substrate in such a manner that at least one part of the contour of the first mark is offset from that of the second mark, and is spaced a minute distance from it, and (c) in forming a third pattern on the substrate, positioning and printing a third alignment mark contained in a third pattern in such a manner that a part of the contour of the third alignment mark is offset from a part of the contour of the first alignment mark, and at least a part of the other portion of the contour of the third alignment mark is similarly
    Type: Grant
    Filed: December 16, 1981
    Date of Patent: December 27, 1983
    Assignee: Fujitsu Limited
    Inventor: Shuzo Fujimura
  • Patent number: 4423356
    Abstract: An AC memory driving type self-shift type gas discharge panel prevents accidental abnormal discharges caused by deviated abnormal charges. Abnormal charges are significantly accumulated at both ends of a shift channel consisting of a regular arrangement of a write discharge cell and shift discharge cells. Therefore, conductive layers are provided adjacent to at least both ends of the shift channel in order to dissipate the abormal charges.
    Type: Grant
    Filed: May 28, 1982
    Date of Patent: December 27, 1983
    Assignee: Fujitsu Limited
    Inventors: Sei Sato, Masayuki Wakitani, Kenichi Oki, Shoshin Miura, Hisashi Yamaguchi, Yoshinori Miyashita, Tsutae Shinoda, Kazuo Yoshikawa, Kurahashi Keizo, Toyoshi Kawada
  • Patent number: 4420874
    Abstract: An I.sup.2 L type semiconductor device having an elementary region which is isolated by V-shape grooves from the other portions of the device, said semiconductor device comprising an insulating layer coating covering the surface of the semiconductor body of the device, wherein an injector region is formed under said insulating layer and surrounded by thicker portions of said insulating layer, and base regions are formed under said insulating layer between said thicker portions of said insulating layer and said V-shape grooves.
    Type: Grant
    Filed: January 18, 1982
    Date of Patent: December 20, 1983
    Assignee: Fujitsu Limited
    Inventor: Tsuneo Funatsu
  • Patent number: 4422038
    Abstract: An integrated circuit having a frequency-dividing circuit which can be tested at high speeds, in which the frequency-dividing circuit is separated into a first stage frequency-dividing circuit and a second stage frequency-dividing circuit, an output buffer circuit and a test signal input circuit are connected to an alarm terminal parallelly, and test signals applied to the alarm terminal are supplied to the second stage frequency-dividing circuit via the test signal input circuit and a switching circuit.
    Type: Grant
    Filed: February 18, 1981
    Date of Patent: December 20, 1983
    Assignee: Fujitsu Limited
    Inventors: Hideo Monma, Masayuki Takahashi, Masato Ishiguro
  • Patent number: 4420691
    Abstract: Electron beam apparatus is used to develop a resist coated work piece such as a semiconductor wafer which is mounted on a moveable XY table within the apparatus work chamber. A work piece holder includes an alignment device for aligning the electron beam for highly accurate beam scanning. Thereafter, the electron beam axes are correlated to the work piece axes. In correlating the axes, the electron beam is rotated whereby the beam X and Y axes are parallel to the work piece X and Y axes, respectively. The work piece axes are then correlated to the axes of the XY table by locating the table coordinates of two known positions on the wafer.
    Type: Grant
    Filed: December 28, 1978
    Date of Patent: December 13, 1983
    Assignee: Fujitsu Limited
    Inventor: John J. Zasio
  • Patent number: 4420823
    Abstract: A static semiconductor memory having a plurality of memory cells respectively connected to word lines and connected in parallel to bit line pairs and having a power-down function, is provided with a coupling noise canceller connected to a data bus which is connected at one end to a bit line via a transfer gate and at the other end to a sense amplifier. When the static semiconductor memory is placed in a power-down mode, the coupling noise canceller operates to clamp the data bus at a predetermined potential; thus preventing an increase in the access time when the chip is accessed from the power-down state rather than the active state.
    Type: Grant
    Filed: December 24, 1980
    Date of Patent: December 13, 1983
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Shimada
  • Patent number: 4420223
    Abstract: An optical apparatus wherein a mirror is mounted on a stage. On such stage a supporting portion is provided and the mirror is fixed such to supporting portion at a single portion of the mirror. At the free end portions of the mirror, which are not fixed to the stage, the end surface is in contact with a buffering member.
    Type: Grant
    Filed: November 27, 1981
    Date of Patent: December 13, 1983
    Assignee: Fujitsu Limited
    Inventors: Yoshio Watanabe, Nobuo Iijima
  • Patent number: 4420730
    Abstract: A surface acoustic wave filter which comprises: a substrate of piezoelectric material; a multistrip coupler for changing the track of a signal comprising a plurality of parallel conductive strips; at least two transducers disposed on one side of the multistrip coupler; at least another two transducers disposed on the other side of the multistrip coupler. The latter two transducers facing the former two transducers. One pair of the transducers which face each other through the multistrip coupler constitutes input transducers while the other pair of the transducers constitutes output transducers.
    Type: Grant
    Filed: October 23, 1981
    Date of Patent: December 13, 1983
    Assignee: Fujitsu Limited
    Inventors: Noboru Wakatsuki, Yuji Kojima, Masaaki Ono