Abstract: A logical circuit which is capable of serving not only as a shift register but also as counter, comprises a cascade-connection of flip-flops of the same number as the number of bits required. The flip-flops have an input connected to a logical gate group composed of gates which are opened and closed by a shift signal and a count signal. The logical circuit does not require that a flip-flop be included for each shift register part and counter part for each bit, but only requires one flip-flop to perform both the count and shift function. The logical circuit is capable of performing an independent operation of a shift register, an independent operation of a counter and a compound operation of inputting data in a serial fashion for initialization and outputting counted data in a serial fashion.

Abstract: A direct imaging method wherein a recording electrode comprising a plurality of electrode styli and a magnetic toner developer are provided on opposite sides of an insulating recording medium, such that an image is printed on the recording medium through direct adherence of magnetic toner on the recording medium when a voltage is applied across the recording electrode and magnetic toner developer. A proper gap discharge is generated between the recording electrode and the recording medium by forming a very narrow gap between the recording electrode and the recording medium. The present invention also comprehends adhering charges to the rear side of the recording medium by means of such gap discharge and the magnetic toner of the magnetic toner developer is reliably held to the surface of the recording medium by means of such charges.

Abstract: A method for automatic frequency adjustment of mechanical resonators, in which plural target frequencies are specified spaced across the distribution curve of the initial resonance frequencies of the mechanical resonators; an output quota for finished resonators is specified at each target frequency; the initial resonance frequency of each resonator is measured, and the resonator is then transferred to an automatic trimming machine; and the adjusting frequency of the automatic trimming machine is reset, for that particular resonator, to the particular one of the target frequencies which is next higher than the initial resonance frequency of the mechanical resonator. However, if the output quota for that target frequency has already been filled, a still higher target frequency is specified instead. If the output quotas have been filled for all target frequencies within a permissible adjustment range, then the resonator is returned for coarse adjustment.

Abstract: In a buffer memory for a swap data block storage system, in the writing of data in an area of a size equal to or an integral multiple of a block of the buffer memory, when it is detected that a block including an address at which data to be written does not exist in the buffer memory, data is written in a replace block of the buffer memory directly without conducting at least an operation of moving out a block from a main memory.

Abstract: A decoder circuit comprises input gates, a logic circuit for generating an output according to input signals, an output gate for driving a word line, and a current control device for activating the output gate according to the output of the logic circuit.

Abstract: A method of plasma enhanced chemical vapor deposition of a phosphosilicate glass film on a substrate from a reaction gas mixture including SiH.sub.4, N.sub.2 O and PH.sub.3 is disclosed. This deposition is effected under the conditions such that a mol ratio of N.sub.2 O to SiH.sub.4 (N.sub.2 O/SiH.sub.4) in the reaction gas mixture is 50 or more and that a mol ratio of PH.sub.3 to SiH.sub.4 (PH.sub.3 /SiH.sub.4) in the reaction gas mixture is 0.08 or less. In the phosphosilicate glass film thus deposited, no cracking occurs due to a high temperature heat-treatment and due to the stress, caused by cooling the deposited films to an ordinarily ambient temperature.

Abstract: A spinner comprises a rotating spindle for causing a workpiece to spin at a high speed, and a cup disposed around the spindle and provided at a bottom wall thereof with a port for air evacuation. The cup comprises a deflector ring disposed in the interior of the cup and extending inwardly, the deflector ring having an annular barrier at the inner peripheral edge for defining steps projecting from the upper and lower surfaces of the ring, respectively, and the barrier having an inner peripheral surface formed to diverge at least upwardly with respect to the axis of the spindle.

Abstract: A phase synchronizing circuit, wherein two phase detectors are used in quadrature to detect the phase of an input signal and to avoid hang-up when the phase of the input signal changes abruptly by 180.degree.. The two detected phase signals are then multiplied by a locally generated reference signal and re-combined, so that a synchronized output signal having reduced phase jitter results. This circuit is also incorporated in an N-phase PSK system, where it is used as a synchronizer and not as a demodulator. In a receiver for such a PSK system, the frequency of the received signal is multiplied by N, the phase synchronizer circuit of the invention is then used to extract the carrier (at a N times higher frequency), and a divider is then used to convert the synchronized carrier provided by the synchronizer circuit of the invention down to the original frequency.

Abstract: In order to selectively reduce the etching rate of the polyimide resin layer, ion implantation is carried out thereto. Preferably, the impurity ion such as As.sup.+, P.sup.+, B.sup.+, BF.sub.2.sup.+ is implanted with dosage of 1.times.10.sup.14 cm.sup.-2 or more. As a result, the polyimide resin layer has a resistivity to etching by the etchant containing hydrazine. This method can be used for preventing generation of unwanted etching in the process of forming the via hole in case of using the polyimide resin as the interlayer insulator for multiwiring structure.

Abstract: An error-correcting system is disclosed, which is located between a main memory and a central processing unit. The system includes a relief bit memory, an ECC or Error Correction Code logic circuit, a switching circuit and a correction controlling circuit. The ECC logic circuit detects the occurrence of a soft error and a hard error. When a hard error occurs in the memory, the defective memory cell thereof is switched to the relief bit memory. Accordingly, data to be written into the main memory or the relief bit memory is switched by means of the switching circuit. Similarly, data to be read from the main memory or the relief bit memory is also switched by the switching circuit. The data to be stored in the relief bit memory is validated by means of the ECC logic circuit and the switching circuit. Further, the (n+1)-bit soft and hard errors are reduced to n-bit soft and hard errors by means of the ECC logic circuit and the switching circuit.

Abstract: A semiconductor memory circuit is provided with a right memory cell group and a left memory cell group, word decoders corresponding to respective rows and; which are located between the right and left memory cell groups and which specify an address in the word direction of these memory cell groups, and column decoders corresponding to respective column which specify an address in the bit direction of these memory cell groups. The memory circuit also includes right and left memory cell group selection and drive gates for every word decoder and circuits for detecting whether the accessed memory cell is in the right or left memory cell group. The right or left memory cell group selection and drive gates operate in a complimentary manner and in accordance with the accessed memory cell being in the right or left memory cell group.

Abstract: A sample and hold circuit for holding a sampled voltage, having a first MOS transistor for sampling the input voltage and a holding capacitor for holding the sampled voltage, and further comprising a second MOS transistor. The source and the drain of the second transistor are both connected to the output terminal of the circuit. The gate-source capacitance of the first MOS transistor is the sum of the gate-source and gate-drain capacitances of the second MOS transistor. When a voltage for turning on or off the first MOS transistor is applied to the gate of the first MOS transistor, the second MOS transistor is turned off or on respectively. The effect of this invention is that the sampled voltage can be held constant while turning off the first MOS transistor.

Abstract: An address buffer circuit which generates a pair of complementary signals for selecting a memory cell according to an address input signal is disclosed. This address buffer circuit comprises a short circuit device connected between a pair of output terminals for the complementary signals. During the stand-by period of a memory, the short circuit device electrically connects the pair of output terminals, so that the potential of both of the pair of output terminals becomes an intermediate level between high and low levels provided at the output terminals during the active period of the memory.

Abstract: A prism polarizer comprising a pair of anisotropic crystal prisms faced to each other. Each of the crystal prisms comprises a crystal which has an optical characteristic such that the difference between the square of the refractive index for extraordinary rays and the square of the refractive index for ordinary rays is larger than 1. The angle of incidence of a beam upon the facing plane of the pair of prisms is equal to the Brewster angle for the refractive index for P-polarization rays. P-polarization rays are transmitted through the facing plane. S-polarization rays are totally reflected at the facing plane. Thereby, the incident beam is separated into two polarized beams. Each of the pair of prisms is formed so that each polarized beam is totally reflected within each prism and that the separated outlet beams from the pair of prisms are parallel with each other.

Abstract: In a Schmidt trigger circuit for delaying a signal, means are provided to reduce an undesirable time lag in the discharge of charges stored in a node. The node of interest is connected to the gate of a feed-back transistor to supply a bias voltage to its gate. The node may be charged up to a high level by an abnormal rise of the power source level, and be held at that high level regardless of a subsequent lowering of the power source level to cause a time lag in the lowering of said high level at the time of discharging said charges stored at the node. Such delay is undesirably large. To reduce said time lag a transistor is connected between the node and the power source line such that when the level difference therebetween exceeds the threshold voltage of the transistor, the transistor is turned ON to discharge therethrough charges of the node to the power source line.

Abstract: A semiconductor memory device wherein a redundancy memory cell array incorporated with main memory cell matrixes is disclosed. Memory cells of the main memory cell matrixes are selected by first and third decoders while memory cells of the redundancy memory cell array are selected by second and third decoders. When the redundancy memory cell array is selected by the second decoder, the transmission of a clock signal to the first decoders is stopped by a switching circuit.

Abstract: A semiconductor memory device includes in its chip a decoder circuit which receives external selection signals for selecting a memory chip. The decoder circuit performs the selection of the memory chip in accordance with a logic corresponding to the combination of the external selection signals. The selection logic can be changed by the user of the semiconductor device.

Abstract: A semiconductor device wherein a semiconductor element is bonded with brazing material on a metalized layer formed on an insulating substrate, with lead wires being used to connect the electrodes of the semiconductor element to the metalized layer. An element bonding area and lead wire connecting areas are provided on the metalized layer and are separated, at the inside of an aperture provided in a sealing member which seals the semiconductor element, by separation regions. Therefore, the brazing material used for securing the semiconductor element to the metalized layer does not flow up to the lead wire connecting areas, thus improving the manufacturing yield and reliability of the semiconductor device.

Abstract: A substrate bias-voltage generator is comprised of an oscillator, and a charge pumping circuit, driven by the oscillator via a coupling capacitor, which transfers accumulated electric charges, out of the semiconductor substrate. The oscillator frequency is varied in accordance with the variation of the voltage level of the semiconductor substrate, preferably by means of an RC circuit, fabricated by a MOSFET variable resistance (R) and a capacitor (C), within a ring oscillator or a multi-vibrator. The gate electrode of the MOSFET variable resistance is directly connected to the semiconductor substrate.

Abstract: In a boat with wheels for carrying semiconductor substrates, the friction surfaces of the wheel systems are coated with a silicon nitride film to prevent seizure from occurring during a diffusion, oxidation or annealing process for semiconductor substrates.