Abstract: A process for manufacturing a semiconductor device comprises the step of annealing a porous passivation layer which is deposited on the surface of the device and which covers metallization layers fabricated thereon, by irradiating a laser beam on the passivation layer so as to densify the passivation layer, while the laser beam scans the surface of the passivation layer.

Abstract: An improved contact hole in a method of producing a semiconductor device by forming a silicon dioxide insulating layer by a chemical vapor deposition method on a semiconductor substrate, forming a contact hole in the insulating layer diffusing phosphorus or boron impurities into a portion of the insulating layer around the contact hole, heating the substrate to cause plastic flow of the insulating layer; and forming a conductive layer on the insulating layer, wherein the portion of the insulating layer containing a high concentration of phosphorus or boron plastically flows during the heating step.

Abstract: A method for forming a field isolation structure for a semiconductor device, in which a groove is formed in a semiconductor substrate, an insulating layer is formed on the substrate at least in the groove, a glass layer or a silicon layer is formed thereon, and thereafter a high energy beam such as a laser beam is irradiated onto the glass or silicon layer to selectively heat the same thereby to melt or fluidify the layer and let the same flow into the groove is disclosed. A smooth and flat surface is obtained through the above melting process, which also prevents electrical breaks in wiring layers formed thereon. The method is particularly suited to producing small field isolation structures thus improving the integration density of the device.

Abstract: An electromagnetic relay comprising a box-shaped relay case having an upper opening for accommodating therein an electromagnet, a group of resilient contacts and an operation card, and a relay cover for covering the case. The relay case and cover comprise insulated partition walls for separating the electromagnet from the group of resilient contacts. The partition walls are integrally formed with the relay case and the relay cover respectively, and overlap each other when the relay cover is engaged with the relay case. The use of the partition walls provides for an increased withstand voltage for the electromagnetic relay. In addition, the relay has a coil with grooved coil bobbins capable of receiving coil terminals in such a way that the electromagnetic relay may be mounted either in a direction parallel or perpendicular to the base of the relay case.

Abstract: An improved semiconductor memory device is provided, which has: (i) a first gate electrode in an electrically floating state, at least a part of which confronts a channel region of a semiconductor device and which is separated by an insulating layer from the channel region; (ii) a second gate electrode (i.e., a control electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode; and (iii) a third gate electrode (i.e., an erasing electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode. The insulating layer, separating at least a part of the erasing electrode from the first gate electrode, has a thickness (usually 50 to 300 A) sufficient to allow the passage of charges from the first gate electrode to the erasing electrode through a tunneling effect, thereby discharging the first gate electrode.

Abstract: In a process for producing a semiconductor device, buried regions are formed within the semiconductor substrate by introducing an impurity, an epitaxial layer is formed on the buried regions, and an energy beam is selectively irradiated on the surface of the epitaxial layer.

Abstract: A photomask comprises a transparent substrate on one surface of which a mask pattern is formed of a photoshielding film and the opposite surface of which is roughened in order that rays of incident light are refracted diffusedly through the rough surface and the images of minute particles of dust disappear in the projected pattern.

Abstract: A dead lock releasing method automatically releases a dead lock state in a data processing system, wherein a plurality of kinds of tasks selectively use a plurality of common resources. When one task X occupies a resource A and, in this state, the task is to occupy a resource B, if the resource B is occupied by another task Y, the task X is placed in a waiting state. When the task X is placed in a waiting state based on the occupation of the resource B by the task Y and the task Y, which is to occupy the resource A, is placed in a waiting state based on the occupation of the resource A by the task X, the task X and the task Y are placed in a dead lock state. When the dead lock state is caused between the tasks X and Y, the occupation of the resource A by the task X is released and the processing of the task Y is carried out. Then the processing of the task X is carried out.

Abstract: The present invention discloses a semiconductor memory device composed of double gate type field effect transistors which have control gate and floating gate for accumulating charges. The conditions for optimum charge injection writing and for optimum reading of this semiconductor memory device are mutually inconsistent. In order to satisfy said two conditions, the present invention provides a charge injection transistor and a read transistor, wherein the floating gate of both transistors are electrically connected, the control gates are connected to a first signal lines, the drains are connected respectively to the different second and third signal lines and the sources are grounded.

Abstract: A semiconductor memory circuit having reduced read-access time and comprising a plurality of first and second common line pairs, each including a bit line and a data line connected in series is disclosed. Conventional static RAM memory cells are connected between each of the bit line pairs. A write-control circuit and sense amplifier are connected between each of the data bus pairs. At least one bypassing transistor is connected between each of the first and second common line pairs for conducting current between each of the lines of the common line pairs, thus reducing the read-access time.

Abstract: A nonvolatile memory, especially an electrically erasable and programmable read only memory (EE-PROM) includes an array of memory cells. In each of the memory cells four transistors are formed, that is a read transistor and a first selecting transistor connected in series, and a write-erase transistor and a second selecting transistor connected in series. The write-erase transistor has a floating gate partially provided with a thin insulation layer thereunder. The read transistor also has a floating gate provided with a thick insulation layer thereunder. The first and second selecting transistors are turned to ON or OFF together.

Abstract: A virtual machine system is provided with a control program for concurrently operating a plurality of OSs (Operating Systems). The object is to suppress the overhead produced when simulating privileged instructions for controlling program status words (PSWs). For this purpose, there is provided simple hardware, in place of the software control conventionally used, including a modification register for storing information required to modify the current PSW information and a pending register for storing pending interrupt information for communication to the corresponding OS.

Abstract: A static type semiconductor RAM device comprising a latch circuit at every column which detects, amplifies and temporarily memorizes a read-out signal from each of the memory cells in the corresponding column and which has a large drive capacity. In the static type RAM device according to the present invention, each of the memory cells is used as an element which only holds information, and data bus lines are driven by the latch circuits having a large drive capacity, so that the slow down of the read-out speed and the decrease of reliability of read-out data of the static type RAM device having a large memory capacity is prevented.

Abstract: A magnetic bubble memory device comprising a cassette holder provided in a main bubble memory apparatus and a magnetic bubble memory cassette which is inserted into the holder so as to be electrically connected with a bubble actuating circuit provided in the main bubble memory apparatus. The device further comprises a detector means for detecting the operation of ejecting the cassette from the holder. The detector means transmits a signal for stopping the bubble motion in advance of the disconnection of the cassette from the bubble actuating circuit.

Abstract: In order to improve the operable frequency of a programmable counter circuit which serves as an N-step counter by loading an initial value N, load terminals of flip-flops of respective stages forming the counter circuit are sequentially cascade-connected via buffers and a load signal is applied to each of the load terminals from a load signal generator circuit. The load signal generator circuit includes a detector circuit which detects a specified value which is provided a short time before the initial value loading of the counter circuit and generates a detected output signal. The detected output signal is shifted by a shift register included in the load signal generator circuit which operates on the same clock signal as that which drives the counter circuit, thereby generating the load signal at the moment of the initial value loading of the counter circuit.

Abstract: First and second optical latent image forming devices form an electrostatic latent image directly on a homogeneously charged recording medium surface. Each of the first and second optical latent image forming devices has the capability of discharging almost half the initial charges of the recording medium. The discharging effect of the first and second optical latent image forming devices forms the combined electrostatic latent image.

Abstract: A plural layered wiring which comprises a plurality of polycrystal semiconductor layers can be improved in its magnitude of circuit integration, when one or more upper polycrystal semiconductor layers which is or are doped to a moderate impurity concentration is or are utilized as resistor elements, the lowest polycrystal semiconductor layer which is highly doped is utilized for electrodes and/or wirings for active elements, and both polycrystal layers are connected with each other by regions which are highly doped by upward diffusion of impurities contained in highly doped regions of a substrate, because this configuration entirely avoids the restriction that is imposed for the location of resistor elements arranged in the upper layers. This arrangement is realized by a specific sequential combination of steps which includes a step of upward diffusion of impurities from the highly doped regions of the substrate. An additional advantage of this method is the exclusion of a so-called non-butting process.

Abstract: An integrated injection logic (I.sup.2 L) memory where sink currents flowing into non-selected memory cells are supplied from clamp circuits, not from the selected memory cell. In addition, the potential of the selected bit line through which a write current flows is decreased by the clamp circuits.

Abstract: A semiconductor memory device of a dynamic type, including a read/write circuit in a column circuit in which a data input pin and a data output pin are common. The read/write circuit comprises a data-output buffer (DOB) connected through a three-state circuit (Qa, Qb) to the common data input/output terminal (I/O), and a data write-in buffer of a dynamic type having a latching function and being connected between the common data input/output terminal and data buses, for providing latched data to the data buses. By utilizing a rise or a fall of a write enable signal or a column address strobe signal applied to the memory device, the three-state circuit is set to be a high impedance, and then, write data is latched into the data write-in buffer.

Abstract: An address buffer circuit for comverting an address signal (A.sub.i) of a TTL level into an address signal (A) of a MOS level an its inverted signal (A) comprising: a pre-amplifier (P-AMP) for receiving the address signal having a TTL level; a main amplifier (M-AMP) comprising a flip-flop (FF.sub.3), a circuit for defining the operation of the flip-flop (FF.sub.3); and an output circuit (OUT) comprised of another flip-flop (FF.sub.4) for producing the address signals of a MOS level. In the pre-amplifier, a depletion type transistor (Q.sub.34) is used as a reference constant current source, which is independent of a power supply voltage (V.sub.DD), for the two values of the address signal of a TTL level.