Abstract: A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma.

Abstract: A nonvolatile latch circuit includes: a latch circuit part; a charge absorption circuit part; and a first ferroelectric capacitor having a first electrode connected to a plate line and a second electrode connected to the charge absorption circuit part, wherein when information is read from the first ferroelectric capacitor to the latch circuit part, the plate line is operated to cause the charge absorption circuit part to absorb at least part of charges outputted from the first ferroelectric capacitor so as to suppress variation in potential of the second electrode of the first ferroelectric capacitor.

Abstract: An SRAM macro operates in a normal operation mode in which a plurality of memory-cell array blocks are accessible and in a low power mode in which bit lines in the memory-cell array blocks are left floating. When the SRAM macro returns from the low power mode to the normal operation mode, the bit lines in only memory-cell array blocks to be accessed among the plurality of memory-cell array blocks are precharged in sequence. This allows the peak of precharging current flowing into the SRAM macro to be dispersed.

Abstract: A hard mask formed above a gate film is patterned with a first mask pattern, the patterned hard mask film is processed into a gate pattern with a second mask pattern, the gate film is patterned with the hard mask film as a mask, a spacer insulating film is formed, a third mask pattern covering an edges of the gate pattern is formed above the spacer insulating film, the spacer insulating film is etched with the third mask pattern as a mask, and a sidewall insulating film is formed on side walls of the gate film leaving the spacer insulating film in a region of the edge of the gate pattern.

Abstract: A semiconductor device includes a first device isolation insulating film defining a first region, a first conductive layer of a first conductivity type formed in the first region, a semiconductor layer formed above the semiconductor substrate and including a second conductive layer of the first conductivity type connected to the first conductive layer and a third conductive layer of the first conductivity type connected to the first conductive layer, a second device isolation insulating film formed in the semiconductor layer and isolating the second conductive layer and the third conductive layer from each other, a gate insulating film formed above the second conductive layer, and a gate electrode formed above the gate insulating film and electrically connected to the first conductive layer via the third conductive layer.

Abstract: A recessed portion is formed around an outer edge of a device wafer at a peripheral edge portion of a first face of the device wafer. A recessed portion is formed around an outer edge of a support substrate, at a bonding face of the support substrate. The first face of the device wafer and the bonding face of the support substrate are bonded together by an adhesive. The device wafer is ground from a second face side, on the opposite side to the first face 11, as far as a depth position to reach a bottom face of the recessed portion.

Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.

Abstract: A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.

Abstract: A data scramble device includes an intermediate key generation unit configured to generate intermediate keys from random numbers, and an extended key generation unit configured to generate an extended key from intermediate keys generated by the intermediate key generation unit. Further, the data scramble device includes a scramble arithmetic operation unit configured to generate scramble data by performing a scramble arithmetic operation of target data and an extended key generated by the extended key generation unit.

Abstract: A secure processor system capable of improving the security of processor processing by the addition of minimum modules without the need for a manufacturer and a user to know encryption information of each other has been disclosed. The secure processor system includes a secure processor having a CPU core that executes a instruction code, an encryption key hold part that holds a processor key, and an encryption processing part that encrypts or decrypts data input/output to/from the core with a processor key and a memory, and the encryption key hold part includes a hardware register that holds a hardwired encryption key, a write only register that stores an encryption key for instruction to be input and holds the stored encryption key for instruction so that it cannot be read, and the encryption key hold part outputs a hardware encryption key as a processor key at the time of activation and outputs a command encryption key as a processor key after a encryption key for instruction is written.

Abstract: A wireless station includes a first wireless communication circuit, a second wireless communication circuit, and a control circuit. The first wireless communication circuit communicates by a first wireless communication system in a first cell which includes a first service area, and the second wireless communication circuit communicates by a second wireless communication system in a second cell which includes a second service area narrower than the first service area. The control circuit switches a communication system between the first wireless communication system and the second wireless communication system to control communication. When switching the communication system between the first wireless communication system and the second wireless communication system, the control circuit controls the first wireless communication circuit and the second wireless communication circuit to set a communication system which is used before the switching to an idle.

Abstract: A method can include applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt); applying an array power supply voltage to cells of the SRAM that is near or below Vt; and in a write operation, reading data from at least a first group of the cells that is interleaved with a second group of the cells, and applying the read data to the bit lines of the first group of cells, while write data is applied to the bit lines of the second group of cells.

Abstract: An authentication system includes a device to be authenticated and an authentication device. The device to be authenticated includes a first communication unit configured to transmit an instruction code and a first comparison value, and to receive a random number, a first memory unit, and a first control unit configured to create the first comparison value based on the random number, the common secret identification information and the instruction code. The authentication device includes a second communication unit configured to transmit the random number and to receive the instruction code and the first comparison value, a second memory unit, and a second control unit configured to generate the random number, create a second comparison value, compare the first comparison value with the second comparison value, and execute the instruction code when the first comparison value matches with the second comparison value.

Abstract: A method for file access includes accessing, by a processor, a file which is divided and stored in data area including a plurality of access units on the base of an access unit management table, the accessing including using a first table included in the access unit management table, the first table including a first management information corresponding to a first access unit and indicating that the first access unit and a second access unit following the first access unit in chains are located in continuous addresses and a second management information corresponding to the first access unit and indicating that the first access unit and the second access unit are located in discontinuous addresses, and using a second table included in the access unit management table, the second table including access unit identification information of the first and the second access units which are located in the discontinuous addresses.

Abstract: Disclosed is a simulation method for simulating an operation of a device. The simulation method includes specifying, by a computer, a boundary between a non-defective status and a defective status of a product in design space with a design parameter as an origin. The boundary is specified according to a search using a search indicator defined based on an operating state different from an operating state of a determination indicator that determines the non-defective status and the defective status of the operation.

Abstract: A receiver includes a transformation part configured to convert a time domain received signal to a frequency domain signal, a known signal extraction part configured to extract a known signal from the frequency domain signal, an estimation part configured to estimate a channel characteristic based upon the extracted known signal, a time direction extraction part configured to extract channel characteristic values of a particular carrier in a time direction from the estimated channel characteristic, a power spectrum acquiring part configured to acquire a power spectrum from the channel characteristic values extracted in the time direction, an error calculation part configured to calculate a carrier frequency error from the power spectrum, and a carrier correction part configured to correct for a carrier frequency of the received signal based upon the carrier frequency error.

Abstract: A digital-to-analog conversion circuit includes first current sources weighted depending on lower-order bits of digital input signals and supplied with a first bias voltage and second current sources weighted depending on higher-order bits of the digital input signals and supplied with a second bias voltage. A reference current source circuit generates the first and second bias voltages based on a first reference current. An output circuit combines currents from the first and second current sources in accordance with the digital input signals to generate an output current, the currents from the first and second current sources being set according to the first reference current. A correction circuit changes the first reference current into a second reference current smaller than the first reference current, and adjusts the first and second bias voltages based on currents from the first and second current sources changed according to the second reference current.

Abstract: The present invention provides a semiconductor wafer characterized by including: a silicon substrate which includes chip regions and scribe regions; multiple-layered films formed on the silicon substrate; and a reference mark formed in at least one film constituting the multiple-layered films. In addition, the semiconductor wafer is also characterized in that the reference mark is located at least one of the vertices of a virtual rectangle covering the plurality of chip regions, and in that the reference mark is longer than one side of each of the chip regions.