Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

Abstract: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.

Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

Abstract: A method for processing one or more bursts including receiving at least a portion of a first burst comprising one or more protocol data units. The method includes receiving a sequence number for the first burst. The method includes writing the sequence number and the first burst to a physical-layer queue, such that the first burst is concatenated to the sequence number in the physical-layer queue. The sequence number may identify the first burst from one or more second bursts written to the physical-layer queue preceding or following the first burst.

Abstract: A secure module includes a generating unit that executes generation processing of generating a scanning program that causes scan processing, which generates unique code for a program under test, to be executed at a connected device and further executes update processing of randomly updating contents of the scanning program; a storage device storing therein the unique code for the program under test; and an authenticating unit that if the scanning program is executed by the connected device and executed with respect to the program under test stored at a designated storage area in the connected device, authenticates validity of the program under test stored at the designated storage area, based on the unique code stored in the storage device and execution results of the scanning program executed at the connected device.

Abstract: A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.

Abstract: A method for manufacturing a semiconductor device includes, forming, on a substrate, an element isolation insulating film which includes a protruding portion protruding above a level of a surface of the substrate, forming a first film on the substrate and on the element isolation insulating film, polishing the first film to expose the protruding portion, forming a first resist pattern which straddles the first film and the protruding portion after polishing the first film, patterning the first film using the first resist pattern as a mask to form a first pattern, and forming a sidewall film at side surfaces of the first pattern.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A transmission circuit includes a first path that connects a first terminal for inputting or outputting signals, and one of a pair of second terminals for outputting or inputting the signals; a second path that connects the first terminal and another one of the pair of second terminals; a first circuit including a first capacitor that is serially inserted in the first path, which is configured to perform single-differential conversion on signals transmitted through the first path, to perform impedance matching, and to supply a bias voltage; a second circuit including a first inductor that is serially inserted in the second path, which is configured to perform single-differential conversion on signals transmitted through the second path, to perform impedance matching, and to supply a bias voltage; and a switch that is connected between the two terminals of the pair of second terminals.

Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.

Abstract: The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts.

Abstract: An integrated circuit can include a plurality of drive monitoring sections, each including at least one transistor under test (TUT) having a source coupled to a first power supply node, a gate coupled to receive a start indication, and a drain coupled to a monitor node, at least one monitor capacitor coupled to the monitor node, and a timing circuit configured to generate a monitor value corresponding to a rate at which the TUT can transfer current between the monitor node and the first power supply node; and a body bias circuit configured to apply a body bias voltage to at least one body region in which at least one transistor is formed; wherein the body bias voltage is generated in response to at least a plurality of the monitor values.

Abstract: A method for manufacturing a semiconductor device includes implanting indium into a first region of a semiconductor substrate; forming a first gate insulation film having a first film thickness in the first region and a second region different from the first region after the implanting; removing the first gate insulation film from the first region; applying heat treatment to the semiconductor substrate after the forming; and forming a second gate insulation film having a second film thickness on the first region after the applying. In the method, a temperature falling rate of the heat treatment in the applying is 20° C. per second or higher.

Abstract: When a design apparatus adjusts clock skews, the design apparatus separates each of the power supply currents which flow through circuit sections that operate in synchronization with a clock signal into a plurality of frequency components, sets skew values of the clock signal which reaches the circuit sections, and performs, by changing the skew values, repetition of calculating a combined amplitude by combining, with respect to each of the frequency components, corresponding ones of the frequency components of the power supply currents which flow through the circuit sections and finds dependence of the combined amplitude on a skew.

Abstract: An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.

Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.

Abstract: When a voltage monitoring circuit detects that a supplied voltage is in a state of being less than a certain voltage at a time of performing writing of data with respect to a memory cell of a memory core having a refresh function, a flag is set in a register circuit, an address at which the writing is performed is held, and the memory core is made to execute rewriting by a refresh operation with respect to the held address, in accordance with the flag set in the register circuit, thereby enabling an increase in speed of operation while securing a retention life of memory data, and enabling a reduction in power consumption without lowering a processing capability even if the supplied voltage is lowered.

Abstract: A method of verifying a layout of a semiconductor integrated circuit is disclosed. The method includes executing a timing analysis of the semiconductor integrated circuit based on first layout information acquired after execution of a layout process, executing layout correction with respect to the first layout information, comparing the first layout information acquired before the execution of the layout correction and second layout information acquired after the execution of the layout correction to acquire information indicating an RC difference in wires, and adding, by a computer, an effect due to an increase in delay in the wires resulting from the RC difference to timing information obtained by the timing analysis.

Abstract: A method for manufacturing a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.

Abstract: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.