Abstract: A semiconductor device includes a drift layer having a structure wherein a plurality of quantum dot layers each including a quantum dot containing InxGa1-xN (0?x?1) and a burying layer burying the quantum dot and containing n-type Inx(GayAl1-y)1-xN (0?x?1, 0?y?1) are stacked.

Abstract: An object detection circuit detects an object moving in a periphery of a vehicle by a frame correlation method that uses a plurality of shot images captured at successive times. A state judgment part disables a detection function of the object detection circuit when a steering angle of an own vehicle is not in a prescribed steering angle range. Then, a condition changer changes the prescribed steering angle range corresponding to a condition of the steering angle in accordance with a velocity of the own vehicle. Therefore, the condition changer can relax the condition for enabling the detection function in accordance with the velocity of the own vehicle within a range where detection accuracy is ensured.

Abstract: An observation information processing apparatus calculates, for each mesh, a support and a confidence. The observation information processing apparatus generates an adjacent mesh set by merging adjacent ones of the meshes. The observation information processing apparatus calculates, based on a support and a confidence of each mesh included in the adjacent mesh set, a confidence for each adjacent mesh, and sets the smallest one of the confidences calculated as a new confidence threshold value. The observation information processing apparatus detects and excludes meshes to be excluded from meshes included in the adjacent mesh set, based on the confidences and supports of the meshes included in the adjacent mesh set and the confidence threshold value.

Abstract: An address generator includes a storage device in which one or more second-protocol-family address prefixes are stored, the one or more second-protocol-family address prefixes each corresponding to a corresponding combination of at least a multiplexing identifier and a first-protocol-family address, and a controller configured to read, from the storage device, the second-protocol-family address prefix corresponding to a combination of at least the multiplexing identifier and the first-protocol-family address that is contained in a data block to be transferred via a backbone network to a destination network which uses the first protocol family, the read second-protocol-family address prefix serving as an address prefix for a network that is overlaid with the destination network, and configured to generate a second-protocol-family address containing the first-protocol-family address, the multiplexing identifier, and the read second-protocol-family address prefix, the generated second-protocol-family address ser

Abstract: A method of manufacturing a semiconductor device includes forming a barrier metal film on a surface of at least one of a first electrode of a wiring board and a second electrode of a semiconductor element, providing a connection terminal between the first and second electrodes, the connection terminal being made of solder containing tin, bismuth and zinc, and bonding the connection terminal to the barrier metal film by heating the connection terminal and maintaining the temperature of the connection terminal at a constant temperature not lower than a melting point of the solder for a certain period of time.

Abstract: An RFID tag includes an antenna, a first IC chip connected to the antenna, and a first fuse inserted between the antenna and the first IC chip, or inserted in series with the antenna. In the RFID tag, the first fuse becomes electrically conductive at a first temperature or above, and remains in an electrical conductive state after having become electrically conductive.

Abstract: A wireless communication device includes a memory, and a processor coupled to the memory and configured to extract a control code from a signal received through a first communication system that has lower priority than a second communication system prior to carrying out communication through the second communication system, compare the extracted control code with a given control code stored in the memory, determine whether the extracted control code matches the given control code, and cause a communication device that is configured to carry out communication through the second communication system to stop processing for establishing a wireless communication when the processor determines that the extracted control code does not match the given control code.

Abstract: An image processing apparatus includes an extraction section that extracts a first high brightness region from a source image where brightness is a first threshold value or greater, a mask generation section that performs blur processing and binarization processing on the first high brightness region and generates a mask containing the first high brightness region, a mask application section that based on the mask performs elimination processing, thinning processing, or both on the first high brightness region, a bright line generation section that generates a bright line based on a second high brightness region contained in output of the mask application section, and a synthesizing section that synthesizes the bright line onto the source image.

Abstract: A computing method for a simulation in which an article, a conveyor, and a table are plotted in a three dimensional simulated space, and in which the conveyor conveys the article includes setting a priority representing a degree at which the lifter is handled as a single unit as the article higher than another priority representing a degree at which the table is handled as a single unit as the article when the lifter moves the article placed on the table upwardly, and setting the priority representing a degree at which the lifter is handled as a single unit as the article lower than the priority representing a degree at which the table is handled as a single unit as the article when the lifter conveying the article moves downwardly below the table.

Abstract: A video encoder includes: a predictive vector selecting unit that selects candidates for a first predictive vector for predicting a motion vector in a first direction, and candidates for a second predictive vector for predicting a motion vector for a second direction; a selection information setting unit that sets first selection information for identifying the first predictive vector from among the first predictive vector candidates, and second selection information for identifying the second predictive vector from among the second predictive vector candidates; and a variable length coding unit that performs variable length coding on the first and second selection information. The video encoder applies predetermined code to the second selection information indicating that the second predictive vector candidate obtained from a motion vector in the second direction, for an encoded block corresponding to the first predictive vector is the second predictive vector.

Abstract: A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section.

Abstract: An information processing apparatus includes a switch unit configured to connect some of the arithmetic processing devices and some of the storage devices in accordance with connection information, a first control unit being configured to output physical information converted from the logical information of the arithmetic processing device at the transmission destination and the physical information of the corresponding arithmetic processing device via a transfer path in accordance with the correlation information, a second control unit configured to change the connection information in response to occurrence of a failure of some arithmetic processing device in the system, and to control the switch unit such that the failed arithmetic processing device is replaced with another one included in the plural arithmetic processing devices.

Abstract: A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock.

Abstract: Provided is a photoelectric conversion device which includes a positive electrode, a negative electrode, a photoelectric conversion layer including poly-[N-9?-heptadecanyl-2,7-carbazole-alt-5,5-(4?,7?-di-2-thienyl-2?,1?,3?-benzothiadiazole)] as a p-type organic semiconductor material and fullerene or a fullerene derivative as an n-type organic semiconductor material; and a buffer layer, provided between the positive electrode and the photoelectric conversion layer, including MoO3, in which device the proportion of the p-type organic semiconductor material in a first region being in contact with the buffer layer in the photoelectric conversion layer is higher than the proportion of the p-type organic semiconductor material in the entirety of the photoelectric conversion layer, and the proportion of the p-type organic semiconductor material in a second region on the negative electrode side than the first region in the photoelectric conversion layer is lower than the proportion of the p-type organic semiconducto

Abstract: A method executed by a processor in a computer including the processor and memory includes: trying to allocate a block of the memory by the processor at a request for memory allocation, in a first case in which a result of a judgment on a probability of success or failure of the memory allocation based on a time taken for the processor to perform each of one or more specific procedures indicates that there is a high probability that the memory allocation succeeds; and either trying to allocate the block of the memory by the processor with a delay with respect to the first case, or returning by the processor, without trying to allocate the block of the memory, a reply that the memory allocation has failed, in a second case in which the result of the judgment indicates that there is a high probability that the memory allocation fails.

Abstract: A method for transmitting Downlink Control Information (DCI), a method for blind detection, a base station and terminal equipment, including: a base station generates a DCI, such that a bit length of the DCI of terminal equipment configured with a carrier segment is equal to that of a DCI of the same format of terminal equipment not configured with a carrier segment; the base station transmits the DCI for the terminal equipment configured with the carrier segment in a common search region of a control channel. Or the base station transmits user-specific DCI in a user-specific search region for the terminal equipment configured with the carrier segment, while does not transmit corresponding user-specific DCI in the common search region of the control channel. The bit length of the common search region will not be increased, avoiding the increase of the number of blind detections at the terminal equipment.

Abstract: A phase interpolation circuit includes: a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals; a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals; and a third circuit configured to generate an output signal by combining the first intermediate signal and the second intermediate signal.

Abstract: A verification test is performed on a device containing master and slave units connected via a bus. In the verification test, a first signal is transferred between a first master unit and a first slave unit during a first transfer period while a second signal is transferred between a second master unit and a second slave unit during a second transfer period. The second transfer period overlaps at least a part of the first transfer period. When the first transfer period is longer than a third transfer period, first combination information indicating the combination of the first master unit and first slave unit is stored in a storage unit, in conjunction with second combination information indicating the combination of the second master unit and second slave unit.

Abstract: An apparatus counts, for each piece of data, an access count indicating a number of times of access to the each piece of data for every unit time so as to store a management information element including the access count and identification information identifying the each piece of data. The apparatus deletes, from the plurality of management information elements stored in a memory, a management information element that includes the access count having a value minimum among the plurality of management information elements, when a number of the plurality of management information elements reaches a predetermined number. The apparatus determines whether there is a piece of data that satisfies a condition related to rapid increase of access, based on the access counts included in the plurality of management information elements.

Abstract: A surge protection circuit includes a first terminal that is coupled to a transmission path, a second terminal that is coupled to a PHY circuit to transfer a signal on a physical layer, a clamping unit that is coupled so as to branch from a first line between the first terminal and the second terminal, the clamping unit clamping a voltage applied to the first terminal to a specific clamping voltage, and a first semiconductor switch that is arranged between the second terminal and a branching point at which the clamping unit branches from the first line, the first semiconductor switch having a rectification direction away from the second terminal toward the first terminal, the first semiconductor switch having a higher reverse breakdown voltage than a clamping voltage of the clamping unit.