Patents Assigned to Fujitsu
  • Patent number: 7188735
    Abstract: A rack structure body for a machine includes a frame body provided at one of a front surface side and a back surface side of the rack structure body. The frame body includes a main frame part formed by bending and a sub frame part formed by bending. The sub frame part is installed inside of the main frame part. The frame body has a hollow structure.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Yoshihisa Nakagawa, Hideki Sonobe
  • Patent number: 7190204
    Abstract: A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Kobayashi, Masaki Okuda
  • Patent number: 7189927
    Abstract: An electronic component with bump electrodes includes a surface-protecting insulating film of adequate thickness and bump elements of adequate height, and allows the occurrence of open defects in the manufacturing process to be appropriately reduced. An electronic component with bump electrodes (X1) includes a substrate (11), electrode pads (12) provided on the substrate (11), an insulating film (13) that has openings (13a) in correspondence with the electrode pads (12) and is laminated and formed on the substrate (11), electroconductive connecting elements (14) provided on the electrode pads (12) in the openings (13a), and bump elements (15) that are in direct contact with the electroconductive connecting elements (14) and project from the openings (13a).
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Limited
    Inventor: Seiki Sakuyama
  • Patent number: 7190415
    Abstract: A digital broadcasting receiver for changing a current channel from one channel to another channel when a commercial message is broadcast on the one channel on which a program is being watched. The time after changing the current channel is measured by a timer IC. When a predetermined time has passed, the current channel is returned to the one channel in response to the operation of a switch or the voice input from a microphone by a user. The program on the one channel is recorded in an RAM so that the program can be reproduced when the user wants to watch the program retroactively. As soon as the predetermined time has passed, an audio output processing section forms a voice message and informs the user of the fact from the speaker so as to draw the attention of the user to the fact.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Ten Limited
    Inventors: Shinichi Iwamoto, Toshitaka Yamato, Hideki Kitao
  • Patent number: 7190305
    Abstract: In a radar apparatus, a receiving antenna includes a plurality of antenna elements, each receiving, as a reception signal, radio waves emitted into space and reflected off a target object. An analog signal is obtained by downconverting and putting a bandwidth constraint on the reception signal, and is then converted to a digital signal. Based on the digital signal, a signal processing unit detects the bearing of the target object. The signal processing unit performs processing based on outputs of two sets of the antenna elements.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Ten Limited
    Inventor: Osamu Isaji
  • Patent number: 7189783
    Abstract: A resist pattern thickening material has resin, a crosslinking agent and a compound having a cyclic structure, or resin having a cyclic structure at a part. A resist pattern has a surface layer on a resist pattern to be thickened with etching rate (nm/s) ratio of the resist pattern to be thickened the surface layer of 1.1 or more, under the same condition, or a surface layer to a resist pattern to be thickened. A process for forming a resist pattern includes applying the thickening material after forming a resist pattern to be thickened on its surface. A semiconductor device has a pattern formed by the resist pattern. A process for manufacturing the semiconductor device has applying, after forming a resist pattern to be thickened, the thickening material to the surface of the resist pattern to be thickened, and patterning the underlying layer by etching, the pattern as a mask.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Miwa Kozawa, Koji Nozaki, Takahisa Namiki, Junichi Kon, Ei Yano
  • Patent number: 7191382
    Abstract: When data is read from a disk and stored in volatile memory, check bits are generated and stored in the memory using an algorithm such as cyclical redundancy check (CRC). The CRC algorithm operates on the basis of the bit length in which the data is organized, such as 8 bits. If the data has errors, an error correction code (ECC) algorithm is used to correct the data errors, but the ECC algorithm operates on the basis of symbols having a different bit length, such as 10 bits. To avoid having to re-read the data from the volatile memory to adjust the CRC value, the CRC algorithm is executed on selected mask data developed by the ECC algorithm, the CRC algorithm being executed on the basis of the second bit length to generate a CRC mask. The CRC mask corrects the stored CRC value.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Michael James, Kana Ono
  • Patent number: 7189659
    Abstract: A method for fabricating a semiconductor device comprises the step of depositing an insulation film 32a with a first pressure set in a deposition chamber; the step of gradually decreasing the pressure in the deposition chamber to a second pressure which is lower than the first pressure; and the step of further depositing the insulation film 32b with the second pressure set in the deposition chamber. The insulation film is deposited with the first pressure a little lower than a second pressure set in a deposition chamber, and the insulation film is further deposited with the second pressure lower than the first pressure set in the deposition chamber. Furthermore, the insulation film is not deposited in the state where the pressure in the deposition chamber is extremely low, and an atmosphere in the deposition chamber is unstable. Thus, a semiconductor device having the insulation film with a sufficiently flat surface can be fabricating without using reflow process.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: March 13, 2007
    Assignees: Fujitsu Limited, Spansion LLC
    Inventors: Yoshimasa Nagakura, Hideaki Ohashi
  • Patent number: 7190627
    Abstract: A semiconductor device having a logic circuit, a delay circuit, and a processing circuit, wherein the logic circuit performs a logical operation process and outputs a first signal, the delay circuit delays an input signal and outputs a second signal, in parallel with the logical operation process of the logic circuit, and the processing circuit inputs the first signal and the second signal, and starts a process when both the first signal and the second signal are outputted.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Limited
    Inventor: Takahiko Sato
  • Publication number: 20070052424
    Abstract: A structure of detecting an anomaly of the battery pack (2) including a plurality of battery cells (41a, 41b, 42a, 42b, 43a, 43b) connected in series or in parallel, which detects whether or not an impedance of at least one of battery cells deviates from a stipulated range. Also, a structure to detect whether or not an impedance change of at least one of battery cells exceeds a stipulated range.
    Type: Application
    Filed: December 30, 2005
    Publication date: March 8, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Masafumi Okumura
  • Publication number: 20070055773
    Abstract: The present invention provides a site evaluation system for evaluating a site which consists of one or more pages and a site evaluation program storage medium that stores thereon a site evaluation program for causing a computer system to operate as such a site evaluation system, in which site evaluation that minimizes errors and inconsistency and requires a lower evaluation cost can be performed. The system acquires a temporal change in the numbers of accesses to each of pages constituting a site, identifies a page for which a temporal change in the number of accesses exceeds a predetermined criterion, further acquires a temporal change in a word in the identified page, compares the temporal change in the number of accesses to the identified page with the temporal change of the word, and evaluates the comparison result based on a predetermined criterion.
    Type: Application
    Filed: November 6, 2006
    Publication date: March 8, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Masafumi Fukumoto, Takeshi Kumazawa
  • Publication number: 20070055679
    Abstract: A structured document expansion method converted a structured document into a format enabling easy manipulation by an application. A structured document is expanded into a format for easy manipulation without requiring complex knowledge. A two-stage associative array structure is adopted to enable easy manipulation of various types of data spanning the entire structured document merely through intuitive array operations, and both associative arrays are linked by sequence numbers. The latter-stage associative array can be accessed from the former-stage associative array using element names, and in addition, the latter stage can be made a two-dimensional associative array to represent hierarchical levels.
    Type: Application
    Filed: January 19, 2006
    Publication date: March 8, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Shigeru Yoshida, Satoshi Nakashima, Junichi Odagiri, Takuroh Yamaguchi
  • Publication number: 20070052311
    Abstract: A motor includes a shaft that rotates with a load, and a dynamic pressure bearing that supports the shaft via fluid in a non-contact manner, wherein the dynamic pressure bearing includes three or more radial bearings that are arranged along a longitudinal direction of said shaft and each radial bearing extends around said shaft.
    Type: Application
    Filed: December 28, 2005
    Publication date: March 8, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Nagata, Mitsuaki Yoshida, Yoshiaki Koizumi, Ritsuko Minamisawa
  • Publication number: 20070051668
    Abstract: The present invention relates to apatite that includes metal atoms having a photocatalytic function and other metal atoms, and the metal atoms having a photocatalytic function include metal atoms that absorb energy corresponding to light energy of visible light. By applying the apatite as a base material of various products to be arranged indoors, the photocatalytic function can be exhibited indoors as well.
    Type: Application
    Filed: November 9, 2006
    Publication date: March 8, 2007
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Toshiya Watanabe, Masato Wakamura, Yasuo Naganuma
  • Publication number: 20070054687
    Abstract: A push-to-talk data transmission device that creates and manages groups of participating terminals dynamically. A PoC data transmission device is deployed to support push-to-talk sessions in a prescribed area. This device has a data transmitter that broadcasts a group profile repetitively in the prescribed area. The group profile is a set of parameters that prompt terminals in the prescribed area to send back their respective unique identifiers to join a push-to-talk session. A counter in the PoC data transmission device counts the number of responses returned from the terminals, and the data transmitter broadcasts a new group profile if the number of responses has reached a predetermined threshold.
    Type: Application
    Filed: February 3, 2006
    Publication date: March 8, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Kenichi Akita, Yamato Sakurai, Koujiro Seto, Ryoji Yagi, Junji Takezaki, Takao Inaguma, Takaya Nomura, Makoto Nagaki, Shinji Yamada, Masafumi Maekawa, Futoshi Nakamori
  • Publication number: 20070052038
    Abstract: A semiconductor device that suppresses variation and a drop in the breakdown voltage of transistors. In the semiconductor device in which a logic transistor and a high-breakdown-voltage transistor are formed on one Si substrate, an insulating film which has an opening region and which is thick around the opening region is formed on a low concentration drain region formed in the Si substrate on one side of a gate electrode of the high-breakdown-voltage transistor. The insulating film around the opening region has a two-layer structure including a gate insulating film and a sidewall insulating film. When ion implantation is performed on the low concentration drain region beneath the opening region to form a high concentration drain region, the insulating film around the opening region prevents impurities from passing through.
    Type: Application
    Filed: March 10, 2006
    Publication date: March 8, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Hitoshi Asada
  • Publication number: 20070055774
    Abstract: The present invention provides a site evaluation system for evaluating a site which consists of one or more pages and a site evaluation program storage medium that stores thereon a site evaluation program for causing a computer system to operate as such a site evaluation system, in which site evaluation that minimizes errors and inconsistency and requires a lower evaluation cost can be performed. The system acquires a temporal change in the numbers of accesses to each of pages constituting a site, identifies a page for which a temporal change in the number of accesses exceeds a predetermined criterion, further acquires a temporal change in a word in the identified page, compares the temporal change in the number of accesses to the identified page with the temporal change of the word, and evaluates the comparison result based on a predetermined criterion.
    Type: Application
    Filed: November 6, 2006
    Publication date: March 8, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Masafumi Fukumoto, Takeshi Kumazawa
  • Publication number: 20070053650
    Abstract: An optical transmission device includes: an attenuator that attenuates an optical signal before being input into an optical element by a predetermined attenuation amount determined so that a level of an adjustment optical signal input into the optical element falls within a predetermined dynamic range of the optical element; and a controller that adjusts the predetermined attenuation amount so that a level of the optical signal input into the optical element falls within the predetermined dynamic range.
    Type: Application
    Filed: January 31, 2006
    Publication date: March 8, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Shimada, Takuji Maeda, Kouji Nekoda, Masanori Kondoh, Taro Asao
  • Publication number: 20070054451
    Abstract: The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed.
    Type: Application
    Filed: April 6, 2006
    Publication date: March 8, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Takuji Tanaka
  • Publication number: 20070052393
    Abstract: A apparatus for preventing a malfunction prevents a malfunction during recovery from critical suspend. The apparatus includes: a voltage detection unit 2 detecting a voltage value from a secondary battery 1; a charging time monitor unit 4 outputting a system activation enable signal when a charging time of the secondary battery 1 by a AC adapter 3 is monitored and a predetermined time passes; and a power supply control unit 5 controlling a system power supply according to a voltage value detected by the voltage detection unit 2 and a system activation enable signal generated by the charging time monitor unit 4.
    Type: Application
    Filed: December 29, 2005
    Publication date: March 8, 2007
    Applicant: Fujitsu Limited
    Inventor: Shigeyuki Okayama