Patents Assigned to Fujitsu
  • Patent number: 6304371
    Abstract: Two rare earth-doped optical fibers are connected in series and used to amplify input light. A splitter is installed between these two rare earth-doped optical fibers. The input light is monitored by having the portion of the input light that is branched off by the splitter received by a photodiode. Excitation light output from a laser light source is guided by optical couplers and supplied to the above rare earth-doped optical fibers. A control circuit controls the output light level and, at the same time, stops the output from the laser light source when the input light level drops below a specified threshold value. The gain of the first stage rare earth-doped optical fiber while excitation light is being supplied is larger than the loss that occurs due to branching of the input light by the splitter.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: October 16, 2001
    Assignee: Fujitsu Limited
    Inventors: Hideaki Sugiya, Yoshihito Onoda
  • Patent number: 6304912
    Abstract: A communication apparatus contains a first table having entries each storing a data-link-layer path to a second communication apparatus, and a second table storing a pointer to the entry of the first table, storing the data-link-layer path to the second communication apparatus, corresponding to a network-layer address of one of the at least one other communication apparatus. In addition, a process for determining layer-2 reachability between first and second communication apparatuses, identifies first and second layer-2-connected communication networks to which first and second interfaces of first and second routers are connected, where, on a layer-3 communication path between the first and second communication apparatuses, the first router is located nearest the first communication apparatus and the second router is located nearest the second communication apparatus. When first and second layer-2-connected communication networks are identical, the layer-2 reachability is determined.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: October 16, 2001
    Assignee: Fujitsu Limited
    Inventors: Naoki Oguchi, Tetsumei Tsuruoka
  • Patent number: 6302454
    Abstract: A battery lock mechanism includes a first sliding operation member and a second sliding operation member. When the second sliding operation member is operated, a battery is released from a locked condition. Initially, an operation knob of the first sliding operation member is exposed through a rectangular window. When the first sliding operation member is driven in a first direction, the operation knob of the second sliding operation member is exposed through the rectangular window so that the second sliding operation member becomes movable in a second direction different from the first direction.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: October 16, 2001
    Assignee: Fujitsu Limited
    Inventors: Shinichiro Tsurumaru, Fumio Nakadaira
  • Patent number: 6304571
    Abstract: A multiprocessor type exchange having a switching apparatus and a plurality of line apparatuses each containing a processor. This multiprocessor type exchange introduces a control information cell and, at the same time, has a cell demultiplexing unit in each line apparatus for discriminating whether each cell which is input is a user cell or the control information cell and separating the same. Each processor is constituted so as to perform communication with other processors via the switching apparatus by using the separated control information cell. By such a structure, a high speed bus, call processing processor, etc. of the related art are eliminated, parallel access is made possible, and, at the same time, system expansion is facilitated.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: October 16, 2001
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Watanabe
  • Patent number: 6304964
    Abstract: An appratus and a method for controlling initialization of a processor system having a memory device which reads data based on a memory request signal and outputs the read data to a data bus and having a processor which outputs the memory request signal based on a reset signal, to read an initialization program stored in the memory device. A detector detects the memory request signal output by the processor. A counter counts the memory request signals detected by the detector. A selector which has predetermined data provided, selects the data in accordance with the counting by the counter and outputs the selected data to the data bus as the initiation information.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: October 16, 2001
    Assignee: Fujitsu Limited
    Inventor: Kazuo Nagahori
  • Patent number: 6304557
    Abstract: A method of detecting the network configuration of a communication network in which a plurality of nodes are connected in a ring form, comprises the steps of; enabling a node of the plurality of nodes to store its own node identifier in a specific position of an identifier storing area of a frame, and transmitting said frame along the network in the same direction; enabling each of the plurality of nodes to store its own node identifier in the identifier storing area of said frame and again transmitting said frame in the same direction, and abandoning said frame, according to contents of said frame received from the adjacent node; and enabling each of the plurality of nodes to recognize an arrangement of the plurality of nodes on the communication network, on the basis of contents of the identifier storing area of said frame constantly transmitted and received on the communication network.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: October 16, 2001
    Assignee: Fujitsu Limited
    Inventor: Seiji Nakazumi
  • Patent number: 6304470
    Abstract: In a power supply device supplying, in parallel, power from a plurality of DC/DC converters to a common load, there is provided an output compensation circuit which is provided on an output side of each of the DC/DC converters and compensates for an output voltage drop due to a voltage drop developing across a diode for parallel operation.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: October 16, 2001
    Assignee: Fujitsu Limited
    Inventors: Tomiyasu Isago, Hiromitsu Ogawa
  • Publication number: 20010028611
    Abstract: An optical pickup for an optical storage device includes a stem, a substrate mounted on the stem, and a laser diode mounted on the substrate. The substrate is integrally formed with an optical signal detector and an error signal detector for focusing error detection and tracking error detection. A cap is mounted on the stem so as to accommodate the substrate and the laser diode. A beam splitter unit including a polarization beam splitter and a beam splitting element is mounted on the cap. A hologram for diffracting a reflected beam toward the error signal detector is interposed between the cap and the beam splitter unit. The substrate is biased at a given potential, and has an insulating film opposed to the stem.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 11, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Motomichi Shibano, Akihiko Yabuki
  • Publication number: 20010028392
    Abstract: The control inputs of reset switch elements 41 to 45 are commonly connected to a row reset line 51. In a line black clamp type, cathodes as reset ends of photodiodes (31) of optical black pixels 21 to 23 are commonly connected to a potential averaging line 30. In a frame black clamp type, potential averaging lines are connected similarly to respective pixel rows on the vertical scanning start side of an optical black pixel region, and the potential averaging lines may be commonly connected to each other to operate just like one pixel row. A first block includes a pixel array and a vertical scanning circuit, while a second block includes sample and hold circuits, a horizontal scanning circuit, an amplifier and an A/D converter 19.
    Type: Application
    Filed: February 20, 2001
    Publication date: October 11, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Katsuyosi Yamamoto, Jun Funakoshi
  • Publication number: 20010028536
    Abstract: A head assembly which can prevent an increase in the frictional force between the head and the recording medium, even if the spindle motor is rotated in the reverse direction during start-up of the disk drive. The head assembly includes a suspension having a roundedly bent portion for generating a spring load and a gimbal located on the suspension. A head slider is mounted on the gimbal. The head slider has an air bearing surface, an air inlet end, and an air outlet end. The spring load of said suspension is applied to the head slider at a load point that is offset from a center of gravity of said head slider. Preferably, the offset load point is located between the center of gravity of the head slider and its air inlet end. Additionally, the head slider preferably includes several pads extending from its air bearing surface, and the offset load point can be located at the center of gravity of the pads (as opposed to the center of gravity of the head slider in its entirety).
    Type: Application
    Filed: July 21, 1999
    Publication date: October 11, 2001
    Applicant: Fujitsu Limited
    Inventors: MASAHARU SUGIMOTO, MASAKI KAMEYAMA, TAKESHI OHWE
  • Publication number: 20010028367
    Abstract: Icons indicating operating conditions of each of nodes (computers) constituting a system are individually displayed in the form of a loop. When the total number of the nodes exceeds a total number B of individual displays, nodes corresponding to B are displayed individually, and the rest are displayed in the form of a node collective icon 11. When a forward button 16 is clicked, a display position of each of the node icons revolves clockwise one by one, a node that has been in the node collective icon 11 is displayed individually at a position of a node icon 12, and an node icon at a position of a node icon 13 is contained in the node collective icon 11. By clicking buttons 15, 18 and 19, a clockwise continuous revolving display, a counterclockwise revolving display and a counterclockwise continuous revolving display are performed. Node icons 3 and 14 are highlighted so as to indicate abnormal conditions of the corresponding nodes.
    Type: Application
    Filed: May 1, 2001
    Publication date: October 11, 2001
    Applicant: Fujitsu Limited
    Inventors: Fumio Saitoh, Yukari Itoh, Takahiro Uchiyama, Toru Kiura, Yoshihiro Mizuuchi, Hideki Shimomura
  • Publication number: 20010028418
    Abstract: There is provided a fault repairing method for a liquid crystal display device capable of repairing simply a disconnected portion when a disconnection fault occurs in a display panel. For example, it is on the assumption that the disconnected portion is present in a data bus line. Disconnection repairing contact holes that have a width larger than that of the data bus line are formed in a protection insulating film on the data bus line on both sides of the disconnected portion respectively. Then, a laser CVD film (metal film) for covering inner surfaces of the disconnection repairing contact holes is formed by the laser CVD method, and then respective laser CVD films are connected electrically.
    Type: Application
    Filed: March 28, 2001
    Publication date: October 11, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Kiyoshi Ozaki, Kenichi Nagaoka, Kunio Matsubara, Yoji Nagase
  • Publication number: 20010028077
    Abstract: A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing electrode formed above the dielectric films, wherein the shape of a side wall of the insulating film includes a shape reflecting the outer peripheral shape of a side wall of the electrode facing the side wall of the insulating film. The semiconductor device of high integration, low cost and high reliability can be realized.
    Type: Application
    Filed: March 15, 2001
    Publication date: October 11, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Shunji Nakamura, Akiyoshi Hatada, Yoshiaki Fukuzumi
  • Publication number: 20010028351
    Abstract: A three-dimensional skeleton data error absorbing apparatus is provided, which is capable of rendering an object at a correct rendering position by absorbing an error based on skeleton data calculation. A fixed skeleton portion specifying part 20 specifies a fixed skeleton portion whose rendering position is desired to be fixed, and a skeleton matrix calculating part 40 obtains a coordinate of a fixed position. A skeleton length detecting part 31, a skeleton hierarchy level detecting part 32, and an error absorption priority detecting part 33 of an error absorbing skeleton specifying part 30 select an error absorbing skeleton that absorbs an error. An error absorption calculating part 60 obtains, by inverse matrix calculation, a determinant, which should be satisfied by a skeleton matrix of error absorbing skeleton, based on the matrix calculation results and the coordinate of a fixed position of the other skeletons.
    Type: Application
    Filed: May 4, 2001
    Publication date: October 11, 2001
    Applicant: Fujitsu Limited
    Inventors: Masatoshi Arai, Ryosuke Miyata
  • Publication number: 20010028785
    Abstract: A broadcast video image recording apparatus for recording broadcast video image data has a first storage unit for storing broadcast video image data, a second storage unit for storing video image data to be played back, and a control unit for searching the first storage unit for video image data which has been indicated, and storing the indicated video image data in the second storage unit. Broadcast video images are stored in the first storage unit at all times, and video images stored in the first storage unit are read and stored in the second storage unit at a time indicated for recording. Therefore, video images that have been broadcast in the past can be recorded.
    Type: Application
    Filed: June 22, 1998
    Publication date: October 11, 2001
    Applicant: Fujitsu Limited
    Inventor: YOSHIYUKI OKADA
  • Publication number: 20010028755
    Abstract: An optical processor of a wavelength-division multiplex optical signal includes a non-linear optical device having an active layer containing therein a number of self-organized quantum dots with respective absorption wavelengths. The quantum dots collectively form a continuous optical absorption spectrum in the wavelength range of the wavelength-division multiplex optical signal.
    Type: Application
    Filed: January 8, 2001
    Publication date: October 11, 2001
    Applicant: FUJITSU LIMITED
    Inventor: Tomoyuki Akiyama
  • Publication number: 20010028417
    Abstract: To provide a liquid crystal display device which allows disconnection defects caused in the manufacturing process to be readily repaired with a higher success rate than conventional cases so that the device can be modified into a non-defective device, and a defect repairing method therefor. In a liquid crystal display device having a lead-out portion provided at a lowermost layer bus line 1 formed on a transparent insulating substrate 6, and a pixel electrode layer 3 formed on the lead-out portion through insulating layers 2, 4, an independent intermediate conductive layer 5 is formed between the lead-out portion and said pixel electrode layer 3.
    Type: Application
    Filed: February 6, 2001
    Publication date: October 11, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Kiyoshi Ozaki, Kouji Tsukao, Satoru Kawai
  • Publication number: 20010028266
    Abstract: A variable delay circuit generates a controlling clock signal by delaying a reference clock signal by a predetermined time. A dummy circuit delays the controlling clock signal by a predetermined time to generate a delayed clock signal. A phase comparator compares the delayed clock signal and the reference clock signal in phase. A delay control circuit adjusts the delay time of the variable delay circuit in accordance with a plurality of phase comparison results from the phase comparator, to have the delayed clock signal coincide with the reference clock signal in phase. Performing a single phase adjustment corresponding to a plurality of phase comparison results, prevents a delay in feeding back the controlling clock signal (delayed clock signal) transmitted through the dummy circuit to the phase comparator. This avoids extra operations of the delay control circuit and the variable delay circuit. Thus, jitter in the controlling clock signal is reduced.
    Type: Application
    Filed: April 6, 2001
    Publication date: October 11, 2001
    Applicant: Fujitsu Limited
    Inventor: Nobutaka Taniguchi
  • Publication number: 20010028344
    Abstract: An optical unit of an optical scanning-type touch panel is constructed by providing a light emitting element for emitting infrared laser light, a collimation lens for changing the laser light from the light emitting element into parallel light, a light receiving element for receiving scanning light, a slit plate for limiting incident light on the light receiving element, a polygon mirror for angularly scanning the laser light from the light emitting element, an aperture mirror for limiting light projected onto the polygon mirror from the collimation lens by an aperture and for reflecting the reflected light from the polygon mirror toward the light receiving element, a light receiving lens for focusing the reflected light from the aperture mirror, and a motor for rotating the polygon mirror in a single optical unit main body as one unit.
    Type: Application
    Filed: April 30, 2001
    Publication date: October 11, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Yasuhide Iwamoto, Satoshi Sano, Fumihiko Nakazawa, Nobuyasu Yamaguchi
  • Publication number: 20010028243
    Abstract: On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (P×N+A) 22 wherein each of P, N and A is an integer, A is variable and A<N, a phase comparator 23, and a charge pump 24. A low pass filter 25 having been confirmed to have standard characteristics is externally added to the semiconductor device 20 to construct a PLL circuit to be tested. The frequency divider 22 is of a pulse swallow type and has a control input for setting the integer A at ones in the vicinity of a value in normal use by user. The control input is connected to external terminals D0 and D1 of the semiconductor device 20 for simplifying a test. The semiconductor device 20 is judged whether it is acceptable or not in quality by checking whether or not the PLL circuit enters into a locked state within a given period in each cases of A=A1 and A=A2, where A1<A0<A2 and A0 is a value in normal use by user.
    Type: Application
    Filed: January 11, 2001
    Publication date: October 11, 2001
    Applicant: FUJITSU LIMITED
    Inventor: Kimitoshi Niratsuka