Abstract: A spectral and power shaping mapper for high data rate signaling modem functions in a first mode having spectral and power shaping and using convolutional encoding, a second mode having power shaping, a third mode having power shaping using convolutional encoding, and a fourth mode having straight-forward mapping. Based on data rates and other criteria, incoming bits are grouped together, with a first subgroup of bits used in the first mode to generate two sign vectors (and in the other modes a single vector), a second subgroup of bits used in conjunction with an appended bit in the first, second and third modes to generate at least two magnitude manipulation vectors, and a third subgroup of bits used in a modulus converter to generate a plurality of quotients. The quotients and magnitude manipulation vector(s) are used to select one, two or four sequences of constellation points from a multidimensional constellation depending on mode.

Abstract: A spectral and power shaping mapper for high data rate signaling modem is provided. Based on data rates and other criteria, groups of incoming bits are grouped together, with a first subgroup of bits being used to generate two sign vectors, a second subgroup of bits being used in conjunction with an appended bit to generate two magnitude manipulation vectors, and a third subgroup of bits being used in a modulus converter to generate a plurality of quotients (r.sub.k). The quotients and magnitude manipulation vectors are used to select two or more sequences of constellation points from a multidimensional constellation. The sequences of selected points are combined with the sign vectors to generate four sequences of octets for a shaping selector. The shaping selector, preferably in the form of a convolutional encoder state machine uses criteria such as lowest cost paths and/or lowest average power in order to select which sequence of octets to output.

Abstract: A two-level or three-level probing signal is generated by a transmitter for transmission over a channel and for detection and analysis by a receiver. The two-level probing signal is a signal having a first PCM .mu.-law level over a first frame, and a second PCM .mu.-law level over a second frame. The two-level probing signal when combined with detection and analysis is generally sufficient for determining the presence and order of RB-signaling and PAD attenuation, and the extent of PAD attenuation may also be determined. The three-level probing signal is similar to the two-level probing signal but includes a third .mu.-law level over a third frame. A preferred two-level probing signal is a signal having a PCM .mu.-law level of .+-.975 for a first frame, and a signal having a PCM .mu.-law level of .+-.1023 for a second frame (or vice versa), although other sets of signals such as .+-.1087 and .+-.879 can be utilized. One preferred three-level probing signal is a signal having a PCM .mu.-law level of .+-.

Abstract: A pulse amplitude modulated (PAM) mapper includes a constellation matrix memory which stores indications of a plurality of different constellations, wherein at least one of the different stored constellations is of different dimension than another of the stored constellations. The constellations are used individually or together to support a plurality of different modem data rates. In a preferred embodiment, in addition to the constellation matrix memory, the mapper includes a logic block, a constellation controller, a PAM code generation block, and an output register. The logic block receives incoming bits of information, groups the bits as a function of the desired or agreed upon bit rate as indicated by the constellation controller, and provides a plurality of each group of bits to the PAM code generation block, and one or more sign bits to the output register.

Abstract: A high speed synchronous digital bidirectional data bus system is provided and includes an M-bit unterminated data bus, an unterminated standing sine wave clock bus, and a plurality of integrated circuit bus interfaces. Each IC bus interface is preferably substantially incorporated on a single CMOS LSI chip and includes M bus drivers with associated send data logic, M data receivers with associated receive data logic, and a clock receiver. The output currents of the bus drivers on all of the chips are preferably stabilized so that each driver drives the bus at substantially the same output current. The drivers are preferably complementary polar driven CMOS logic elements. For this case, for each data receiver, a bus keeper is coupled to the output and the input of the bus receiver to maintain the last state of the data bus. In addition, the clock receivers and the data receivers are embodied as high speed comparators having internal hysteresis.

Abstract: An ATM cell switch includes a plurality of link controllers, each of which has a leaky bucket processor to monitor and control cell flow rates. Each of the leaky bucket processors includes a pair of buckets. Each processor times the arrival of each ATM cell in the respective link controller, calculates the time interval between the reception of two consecutive cells on the same connection, simultaneously determines the resultant level in both of the buckets from the calculated time interval and a stored predetermined regular bucket increment, compares the resultant level with a predetermined maximum level, and discards or changes the CLP of the current cell if the resultant level exceeds the predetermined maximum. According to a preferred embodiment of the invention, timing is effected with a 32-bit timer, but only the least significant 16-bits are used to time stamp cells.

Abstract: The invention routes SVC ATM call setups by utilizing one of a plurality of designated transit lists (DTLs) stored at an originating node. The DTLs describe all routes in the network from the originating node to endpoint destinations. When a call setup message is received at the originating node, it inserts a desired DTL as an information element (IE) of the setup message. Each DTL is formatted as a concatenation of elements with each element including the node ID and output ports of each successive node in the route. Preferably, each element of the DTL includes flags such as a "process" flag which indicates whether an element of the DTL has been processed by a node, a "link up" flag which indicates that an alternative route is available between two nodes should the preferred route be down, a "bandwidth" flag which allows the alternate link to be used if the preferred link is busy, and a "last node" flag which is used in the last element of the concatenated DTL.

Abstract: In accord with the objects of the invention, methods and apparatus for controlling communications network equipment are provided. The apparatus is used in a telecommunications network having a plurality of coupled nodes and a network controller coupled to at least one of those nodes, and generally comprises a node apparatus having a backplane and a plurality of functional cards coupled to the backplane. Each of the functional cards has a processor and memory for storing software which is used by the processor. One of the functional cards has memory for storing a current running version of software for each of the other of the plurality of functional cards, and a receiver and memory for storing in background incoming updated versions of software for the plurality of functional cards. The updated versions of software are provided in the overhead portion of the telecommunications signal frame, thereby being non-disruptive to the system.

Abstract: A method and switch appratus for transporting an ATM layer OAM cell across a FUNI are disclosed. The method broadly includes generating a DXI (FUNI) frame from the ATM layer OAM cell by using certain bits of the five byte ATM overhead as bits in the two byte DXI (FUNI) header, using the forty-eight byte ATM OAM cell payload as the payload for the DXI (FUNI) frame, and providing an indication in a predetermined bit field of the two byte DXI header that the forty-eight byte payload is an ATM OAM cell. Preferably, the predetermined bit field includes the previously reserved second lsb of Octet 1 of the DXI frame header, and the previously reserved third lsb of Octet 2 of the DXI frame header, which are set to values of "0" and "1" to indicate an ATM OAM cell, and to "0" and "0" to identify "regular" data.

Abstract: Reservation controllers and reservation systems for reservation of access to multimedia multipoint telecommunications servers (MCUs) are provided. The reservation controller establishes a reservation domain having a reservation request channel on which reservation applications may be taken. An ongoing reservation conference is associated with the reservation domain. The reservation domain is preferably established within the ITU-T T.120 standard series requirements, with multipoint connection under T.122/T.125, and interface to profiles such as ISDN, TCP/IP, X.25, ATM, Ethernet, etc., under T.123. A user makes reservations for MCU resources by knowing the address of the reservation domain, attaching himself to the reservation domain, joining the reservation conference via establishing one or more transport connections, and sending the reservation request onto the reservation request channel.

Abstract: A method for identifying and declaring a physical loopback condition upon running an OAM loopback test is provided. The method modifies ITU-T Recommendation I.610. According to the method, an OAM loopback test cell is generated with a correlation tag and a loopback indication value representing an outbound (forward) test cell, with the correlation tag being stored. Upon receiving back an OAM loopback test cell, the value of the loopback indication is determined, and the correlation tag of the incoming OAM loopback test cell is compared with the stored correlation tag. If the correlation tags match and the value of the loopback indication represents a forward test cell, a physical loopback condition is declared. On the other hand, if the correlation tags match and the value of the loopback indication represents a backward test cell, a successful OAM loopback condition is declared.

Abstract: An isolated, high impedance, DC current source is provided from a readily available AC type source. The DC current source includes an isolating transformer which receives the AC source signal and provides an isolated AC voltage signal therefrom, a resonant low pass filter which is tuned to the frequency of the AC type source and which takes the AC isolated voltage signal and generates therefrom an AC current source signal, and a rectifier which rectifies the AC current source signal to provide a DC current source signal. A voltage limiting clamp is preferably coupled to the rectifier in order to limit the output voltage to a desired level. The resonant low pass filter is preferably comprised of two substantially equally valued inductors coupled to respective poles of the secondary winding of the isolating transformer, and a capacitor which is coupled to both of the inductors.

Abstract: An integrated TDM-based/packet-based telecommunications backplane system includes a multi-bit backplane bus, a plurality of TDM data modules and packet based data modules coupled to the backplane bus, and a frame controller coupled to the bus which generates a frame by pre-assigning a first plurality of timeslots of a frame for the fixed rate TDM traffic, and allotting the remainder of the frame timeslots as a pool for packet-based traffic. The TDM data modules, which can include bit, and byte or nibble mode modules, place data on the backplane bus in their allotted time slots. The packet-based data modules contend for the pooled timeslots by raising a request on a "request" thread of the backplane bus when the packet module has a packet to send, and dropping the request and raising a busy flag on the "busy" thread while sending a data packet.

Abstract: A polled digital multiport, multidrop system is described. The inbound frame for sending information from remote terminals to the host terminals is arranged such that a plurality of bytes are provided by a first terminal, followed by a guard band, followed by a plurality of bytes provided by a second terminal, followed by another guard band, etc. The guard band permits signalling between the DSU and the OCU which in turn permits the OCU to signal the MJU that no data will be coming from the OCU. In this manner, control mode idle is accomplished and data mode idle is avoided. In addition, because of the guard band, if the delay from a remote site changes, no data will be lost. Means for monitoring the system to follow changes in delay are also provided, and the system can cause a remote location to accommodate a change in delay.

Abstract: A clock phase and frequency distribution system is disclosed which uses a standing sine wave and provides substantially simultaneous significant crossing instances everywhere in the system while using low power and not requiring bus termination or precise control of transmission path characteristics (Z.sub.0). The system is particularly advantageous in high frequency applications such as digital, linear (non-branched), backplane applications, but is also applicable to other topographies such as stars, rings, and meshes. The system includes a sine wave generating and driving circuit, a clock bus, and clock receivers. The clock receivers present a high impedance interface to the clock bus.

Abstract: Output characteristics of CMOS chips are controlled by providing a known and stable current to a representative transistor of known relative size in the CMOS chip, and arranging the output CMOS driving transistor(s) of the chip, which are of known size relative to the representative transistor, in current mirror relationship with the representative transistor. Two primary embodiments of the invention are provided. In a first primary embodiment (I.sub.d,SAT stabilization), the representative transistor is a diode-connected transistor with a saturation current which is generated by the current source and which is also provided to drive the output transistor device(s) when it is ON. In the second primary embodiment (R.sub.ON stabilization), instead of being diode-connected, a servo is used to adjust the gate voltage of the representative device until it is greater than the drain voltage by a desired amount. In this manner, the resistance (R.sub.

Abstract: Systems and methods are provided for automatically and remotely establishing a diagnostic channel between a network managed master digital service unit (DSU) and a remote fractional T1 or E1 DSU. In the preferred method, the master DSU sends a priming sequence in all of the DS0s/TS0s of the DS0/TS0 bundle intended for the remote DSU which is comprised of a two second break, followed by a relatively low frequency signal which identifies at least the diagnostic channel for the remote DSU. In response, the remote DSU sends a confirmation signal to the master over the identified diagnostic channel, after which the master DSU can send configuration information over the same diagnostic channel.

Abstract: A sixty-four state convolutional code known as the "Cole code" is disclosed and take systematic and non-systematic forms. The state variables of the Cole code are r(n-1), r(n-2), s(n-1), s(n-2), p(n-1), and x(n-1). In the four-to-five non-systematic form, four inputs p(n), q(n), r(n) and s(n) are used to generate five outputs y.sub.4 (n), y.sub.3 (n), y.sub.2 (n), y.sub.1 (n), and y.sub.0 (n) according to: y.sub.4 (n)=q(n); y.sub.3 (n)=p(n)+r(n)r(n-1)+r(n-2)+r(n-1)s(n)+r(n-1)s(n-2); y.sub.2 (n)=r(n-1)+s(n)+s(n-2); y.sub.1 (n)=r(n)+r(n-1)r(n-2)+p(n-1)+p(n-2)+q(n-1); and y.sub.0 (n)=s(n-1), where p(n-2)+q(n-1)=x(n-1). New state variables are obtained directly from the inputs and from the previous state variables, except for x(n) which is equals q(n)+p(n-1). In a three-to-four non-systematic implementation of the Cole code, q(n) is not input, y.sub.4 is not output, and q(n-1) is set equal to zero. In the four-to-five systematic form of the Cole code, the inputs y.sub.4, y.sub.3, y.sub.2, y.sub.

Abstract: A time division multiplexer (TDM) is provided for multiplexing data from a plurality of channels. The TDM system generally comprises a high speed time division multiplexed digital data bus, a synchronizing bus, a plurality of channel cards coupled between the data channels and the data bus with each channel card having its own processor and memory, and a system communication manager (SCM) which is also coupled to the digital bus, and includes a (micro)processor. The processor of the SCM determines the frame for the system and initially forwards the frame information to each of the channel cards during predetermined time slots of the high speed data bus. The channel cards are synchronized by the SCM via the synchronization bus, and the channel cards use the synchronization information and the framing information in order to appropriately place data on and take data off of the high speed data bus without the use of an address bus.

Abstract: A modem is provided with a Trellis encoder which utilizes a double-branch feedback, with a first branch of the feedback including a convolutional encoder, and a second branch of the feedback including a parity generator which computes the parity of consecutive offsets. The Trellis encoder includes a four-dimensional (4D) mapper which generates pairs of 2D points u(k). Each point is offset by a value c(k) to obtain offset points y(k) which are then predistorted by a value p(k) to obtain an output x(k). The output x(k) is filtered to update the predistortion value p(k) which in turn is used to update the offset value c(k). The offset value c(k) is chosen from a 2D constellation lattice which is closest to the predistortion value p(k). The parity C0 of consecutive offset values c(k) is used in conjunction with a redundant bit output Y0 of a convolutional encoder to generate a rotational feedback bit input U0 to the 4D mapper, where the rotational bit input is the parity of two 2D points chosen by the mapper.