Patents Assigned to General DataComm
  • Patent number: 4926355
    Abstract: A digital signal processor (DSP) for conducting arithmetically complex functions, is provided. The DSP is preferably embodied as a single integrated circuit chip and generally includes a microinstruction sequencer (MIS) section, an arithmetic logic unit (ALU), a serial arithmetic processor section, a RAM section, and a system data bus. The MIS includes a coded ROM, a circuit for addressing the ROM, a ROM decoder for decoding the ROM code into control and data signals, and circuitry for sending the control and data signals to desired locations, and controls the functioning of the DSP. The ALU performs arithmetic and logic functions under the control of the ROM, while the serial arithmetic processor section conducts arithmetically complex functions under the control of the ROM. The RAM, under control of the ROM receives and stores data which is sent to the RAM via a system data bus directly from the ROM, from the ALU, from the serial arithmetic processor, and from circuitry exterior to the DSP.
    Type: Grant
    Filed: July 2, 1987
    Date of Patent: May 15, 1990
    Assignee: General DataComm, Inc.
    Inventor: Charles P. Boreland
  • Patent number: 4922534
    Abstract: An intelligent synchronous modem and data communication systems utilizing the intelligent synchronous modem are provided. The modem comprises: at least one connector having a first and a second port for primary and secondary channels of communication with a host computer, wherein the primary communication channel is for communication of synchronous data and the secondary communication channel is for communication of asynchronous data; a microprocessor for recognizing and executing commands of the host computer, wherein the commands are in the form of asynchronous data received over the secondary communication channnel; and interface means for interfacing the microprocessor with telephone lines, wherein synchronous data received by the microprocessor is sent to the interface means.
    Type: Grant
    Filed: January 30, 1989
    Date of Patent: May 1, 1990
    Assignee: General DataComm, Inc.
    Inventors: Andrew M. Gorniak, Michael J. Fargano
  • Patent number: 4891754
    Abstract: A microinstruction sequencer capable of directing an arithmetic-logic unit to conduct conditional operations is disclosed and generally includes a ROM and a selection circuit. The ROM has a memory of m bits wide and n words long, wherein for an m bit wide word in the ROM which defines a conditional operation, a first plurality of bits of the m bits are allocated to a first set of bits for instructing the arithmetic-logic unit as to the function it is to perform, a second plurality of bits of the m bits are allocated to a second set of bits for instructing the arithmetic-logic unit as to the function it is to perform, and a third plurality of bits of the m bits are allocated to a set of control bits. The selecting circuit selects one set of bits from at least the first and second set of bits, and includes a controller for receiving the control bits and controlling the selection by the selection circuit in response thereto.
    Type: Grant
    Filed: July 2, 1987
    Date of Patent: January 2, 1990
    Assignee: General DataComm Inc.
    Inventor: Charles P. Boreland
  • Patent number: 4891823
    Abstract: An encoder is provided for generating rotationally invariant trellis codes when used with a signal constellation having m subconstellations indexed by j, each subconstellation having a plurality of points, where each subconstellation is a distinct rotation by j(360/m) degrees of another subconstellation such that no subconstellation has a point in common with another subconstellation. The encoder has a state block and a state update block. The state means receives q inputs i, and generates m outputs j, where m=pq and where p and q are integers greater than one and have no common factors. Outputs m are generated according to inputs i and states s of the state block according to j=i mod q and jd=s mod p, where the state block can assume n states, and n=md where d is an integer greater than one and has no common factors with p.
    Type: Grant
    Filed: October 26, 1988
    Date of Patent: January 2, 1990
    Assignee: General DataComm Inc.
    Inventor: Paul D. Cole
  • Patent number: 4888770
    Abstract: An algorithm for ordering selects for a plurality of channels to be multiplexed into a frame is provided. A channel ready counter and a channel select position counter for each of the channels to be multiplexed are initialized. The first and succeeding channel selects are chosen based primarily on the respective values of the channel ready counters such that a channel having a ready counter of relative higher value is always selected before a channel having a ready counter of relative lower value. Where channel ready counter integer values of more than one channel are equal, the select is chosen on the secondary basis of channel rate, with the highest rate channel of the highest ready count contributing first. After a select is made, the ready counter of the selected channel is determined, and the position counters of the channels are decremented by a value corresponding to the number of selects for that channel in the frame.
    Type: Grant
    Filed: October 19, 1988
    Date of Patent: December 19, 1989
    Assignee: General DataComm, Inc.
    Inventor: Kuldip S. Bains
  • Patent number: 4888722
    Abstract: A parallel arithmetic-logic unit (PALU) controlled by a microinstruction sequencer and capable of executing conditional operations in a single pass is disclosed. The PALU generally comprises first and second registers for storing data, a comparator for continually comparing the values in the registers, and an arithmetic-logic core connected to the registers for performing arithmetic, logical and data move operations on the data in the registers. The comparator is preferably an unsigned magnitude comparator which outputs flags indicative of the relative status of the values in the registers. The flags are read by a microinstruction sequencer which then uses the flag information to determine what operation the arithmetic-logic core is to conduct. Preferably, a shifter is also provided between one of the registers and the arithmetic-logic core.
    Type: Grant
    Filed: July 2, 1987
    Date of Patent: December 19, 1989
    Assignee: General DataComm, Inc.
    Inventor: Charles P. Boreland
  • Patent number: 4885745
    Abstract: An algorithm for ordering selects for a plurality of channels to be multiplexed into a frame is provided. The channel select position counter for each of the channels to be multiplexed are initialized. The first and succeeding channel selects are chosen based on the lowest price (highest cost) ready channel, with the price of a channel being equal to the value of the channel select position counter divided by the number of selects for that channel in the frame, and the readiness of the channel being indicated either by an indicator, or by the relative value of the position counter to the initial value of the position counter. Where channel prices are equal, the select is chosen on the secondary basis of channel rate, with the highest rate channel contributing first. After a select is made, the position counter of the selected channel is increased by the total number of selects in the frame.
    Type: Grant
    Filed: October 19, 1988
    Date of Patent: December 5, 1989
    Assignee: General DataComm, Inc.
    Inventor: David P. Gordon
  • Patent number: 4881224
    Abstract: Methods are provided for multiplexing a plurality of channels on to a sub-aggregate of an aggregate line so as to substantially minimize total frame length. In a preferred method, channel data rates are expressed as a sum of a plurality of predetermined subchannel data rates, and the number of times each predetermined subchannel data rate is used to express a channel data rate of a channel to be multiplexed is accumulated. Given a predetermined primary frame rate (P) such as 8Khz for a DACs compatible multiplexer, and a tertiary frame rate (T) chosen as the greatest common denominator of the subchannel data rates, an optimal secondary frame rate (S) may be found by minimizing for a plurality of different secondary frame rates the sum of (P/S) F1 plus (S/T)F2, where F1 represents the number of calls of the primary frame to the secondary frame, and F2 represents the number of calls of the secondary frame to the tertiary frame.
    Type: Grant
    Filed: October 19, 1988
    Date of Patent: November 14, 1989
    Assignee: General DataComm, Inc.
    Inventor: Kuldip S. Bains
  • Patent number: 4877364
    Abstract: This invention relates to an improved captive screw and assembly, and particularly a screw which may be held loosely captive in the threaded hole of a support member. The invention comprises a machine screw or cold formed fastener with an unthreaded interrupted mid-section that separates two spaced-apart threaded portions of the fastener, with both threaded portions of the fastener preferably of a similar thread size, and with the unthreaded mid-section of the screw of a diameter less than the root diameter of the threaded sections. The screw may be completely removed or readily installed into threaded engagement with a female threaded hole in the support member, when necessary, by first manually aligning the fastener axis with the axis of the threaded hole, then rotating the fastener to engage the starting threads of the fastener with those of the female threaded hole, and further continued rotating of the fastener in a conventional manner. The fastener may clamp a panel member to the support member.
    Type: Grant
    Filed: May 26, 1987
    Date of Patent: October 31, 1989
    Assignee: General DataComm. Inc.
    Inventor: Gregory Sorrentino
  • Patent number: 4858163
    Abstract: A serial arithmetic processor arranged to perform the complex arithmetic functions of the Adaptive Differential Pulse Coded Modulation (ADPCM) algorithm. The serial arithmetic processor includes a first common circuit which is arranged to take advantage of the realization that a large portion of the LOG, FLOAT, and ANTILOG functions can be implemented in common hardware. The serial arithmetic processor further includes a second common circuit which is arranged to take advantage of the realization that large portions of the MULTIPLICATION and FLOATING POINT MULTIPLICATION functions can be implemented in other common hardware. A controller is provided for controlling logic and other circuitry in the first and second common circuits depending upon the desired function to be performed.
    Type: Grant
    Filed: July 2, 1987
    Date of Patent: August 15, 1989
    Assignee: General DataComm, Inc.
    Inventor: Charles P. Boreland
  • Patent number: 4856031
    Abstract: A multiharmonic adaptive phase jitter compensator for a high speed modem is provided. The compensator includes an IIR filter for each harmonic of phase jitter for which compensation is desired. The coefficient update of each IIR filter as well as the input to the primary jitter frequency IIR receives identical information from a phase detector which compares an equalized phase corrected signal entering a decision means with the ideal point determined by the decision means. However, the IIRs for the higher harmonics are trained with different information. Thus, the primary jitter frequency as adaptively determined by the first IIR is fed to harmonic computation circuitry. The harmonic computation circuitry then provides an adapted second harmonic to the second harmonic IIR, and adapted third harmonic to the third harmonic IIR, etc. The outputs of all the IIRs are summed, and the cosine and sine of the sum are provided to phase correct the equalized signal before it enters the decision circuitry.
    Type: Grant
    Filed: April 28, 1988
    Date of Patent: August 8, 1989
    Assignee: General DataComm, Inc.
    Inventor: Yuri Goldstein
  • Patent number: 4845735
    Abstract: Methods and apparatus for measuring propagation delay over a line without interfering with data communications over the line are disclosed. A known signal is sent and looped back over a secondary channel, and the loop time is measured. Because the known signal is sent at a non-interfering frequency at the edge of the passband, the loop time minus fixed delay times of the communicating means does not provide a true measure of propagation delay. Rather, the envelope delay distortion must be determined and also subtracted from the loop time. The envelope delay distortion is determined as a function of the utilized non-interfering frequency and the line length, the latter of which may be estimated from the loop time.
    Type: Grant
    Filed: June 14, 1988
    Date of Patent: July 4, 1989
    Assignee: General DataComm, Inc.
    Inventors: Nicholas W. P. Payne, Kiran K. Mistry
  • Patent number: 4841561
    Abstract: A modem which is provided with the operating parameters of a plurality of countries and can be made compatible with the country in which the modem is to be used is provided.
    Type: Grant
    Filed: December 8, 1987
    Date of Patent: June 20, 1989
    Assignee: General DataComm, Inc.
    Inventor: Gregory P. Hill
  • Patent number: 4839542
    Abstract: An integrator is described that is useful in forming low pass, band pass, high pass, and band stop filters. The integrator comprises a transconductance amplifier and a capacitor which is connected between the amplifier output terminal and the amplifier ground. When implemented as a monolithic IC, the integrator gain is fundamentally process independent. A ladder structure comprising one or more of these integrators provides high order filtering characteristics without many of the problems associated with conventional filter devices. In addition, the integrator provides stop band, zero filter characteristics at the filter output terminal when a capacitor is connected across the differential input terminals of the integrator.
    Type: Grant
    Filed: August 21, 1984
    Date of Patent: June 13, 1989
    Assignee: General DataComm Industries, Inc.
    Inventor: Jeffrey I. Robinson
  • Patent number: 4827431
    Abstract: Methods and systems are disclosed for simultaneously measuring three impairments such as phase jitter, amplitude jitter, and noise, to a quadrature amplitude modulated data communication channel. The invention generally comprises: correlating received signals to an ideal constellation point; rotating the received signals and ideal constellation point such that the ideal point lies on the x axis; determining a phase jitter index (cos.alpha.) as a function (x/x.sub.o) of the average x coordinates of the rotated received signals and the rotated constellation point; determining an index of amplitude jitter (m.sup.2) as a function (((x.sup.2 -y.sup.2)/(2x.sub.p.sup.2 -x.sub.o.sup.2))-1) of the square of average x coordinates, the average of the square of the x coordinates, the average of the square of the y coordinates of the rotated received point, and the square of the rotated constellation point; and determining a noise index .DELTA.x.sub.n 2 as a function ((x.sup.2 +y.sup.2 -x.sub.o.sup.2 (1+m.sup.
    Type: Grant
    Filed: January 20, 1987
    Date of Patent: May 2, 1989
    Assignee: General DataComm, Inc.
    Inventor: Yury A. Goldshtein
  • Patent number: 4817147
    Abstract: An intelligent synchronous modem and data communication systems utilizing the intelligent synchronous modem are provided. The modem comprises: at least one connector having a first and a second port for primary and secondary channels of communication with a host computer, wherein the primary communication channel is for communication of synchronous data and the secondary communication channel is for communication of asynchronous data; a microprocessor for recognizing and executing commands of the host computer, wherein the commands are in the form of asynchronous data received over the secondary communication channel and interface means for interfacing the microprocessor with telephone lines, wherein synchronous data received by the microprocessor is sent to the interface means.
    Type: Grant
    Filed: November 18, 1985
    Date of Patent: March 28, 1989
    Assignee: General DataComm, Inc.
    Inventors: Andrew M. Gorniak, Michael J. Fargano
  • Patent number: 4815074
    Abstract: A bit interleaved time division multiplexer for multinode system is provided and includes a high speed bus, a plurality of aggregate common blocks, a plurality of channel common blocks, and a system controller which selects the aggregate and channel common blocks and which is connected to the bus. Each aggregate common block includes an address recognizer, a recorder for obtaining information according to a first frame format from an aggregate line, supplying an intramultiplexer system address for at least one bit of the obtained information, and sending the information accompanied by the intramultplexer system address onto the high speed bus, and a recorder and transmitter for receiving bits of information from the high speed bus, multiplexing the information according to a second frame format and sending the so-multiplexed information out over an aggregate line.
    Type: Grant
    Filed: August 1, 1986
    Date of Patent: March 21, 1989
    Assignee: General DataComm, Inc.
    Inventor: Christian C. Jacobsen
  • Patent number: 4811360
    Abstract: A data communication equipment equalizer which minimizes the total training time delay (RTS-CTS) is disclosed. The total RTS-CTS delay of the provided equalizer consists of a delay due to a minimal training sequence required for the equalizer coefficients to converge given a low distortion channel, plus whatever delay is necessary for the equalizer coefficients to converge given the particular channel.
    Type: Grant
    Filed: January 14, 1988
    Date of Patent: March 7, 1989
    Assignee: General DataComm, Inc.
    Inventor: William J. Potter
  • Patent number: 4809300
    Abstract: A method is disclosed for determining with only sixty-four distance comparisions the distances between a received eight-dimensional vector comprised of four two-dimensional coordinates and each of sixteen non-overlapping subconstellations. In order to limit the comparisons, each subconstellation is represented by a collection of sixteen representational four-coordinate vectors, with each collection having four groups of vectors of the form______________________________________ (a, b, c, d) (a + 2, b + 2, c, d) (a, b, c + 2, d + 2) (a + 2, b + 2, c + 2, d + 2) ______________________________________where each letter represents in a different plane one of a set of points T(0) and its ninety, one hundred and eighty, and two hundred and seventy degree rotations, and +2 represents a one hundred and eighty degree rotation.
    Type: Grant
    Filed: April 5, 1988
    Date of Patent: February 28, 1989
    Assignee: General DataComm, Inc.
    Inventors: Yuri Goldstein, William E. Abdelsayed, Paul D. Cole
  • Patent number: 4803654
    Abstract: A circulating FIFO buffer eliminates the need to move the data through the register and relies instead on input and output counters to load data into the register and read data therefrom. Apparatus comprises an addressable read/write memory, an input counter and an output counter, both of which address the memory, means for resetting the counters, means for enabling the input counter to increment and to load data into the buffer, means for enabling the output counter after a predetermined amount of data has been loaded into the buffer, means for disabling the input counter when the buffer register has been loaded and means for detecting when the outputs of the output and input counters are equal and for activating the resetting means upon detecting such equality.
    Type: Grant
    Filed: June 20, 1985
    Date of Patent: February 7, 1989
    Assignee: General Datacomm Industries, Inc.
    Inventors: Joseph D. Rasberry, Karl D. Nitschke