Abstract: The invention is a shaped base plate assembly onto which one or more separate units may be detachably mounted. One common latch plate, bolted to the base plate, fixes all the separate units in place in fixed relation to each other and to the base plate. The invention may be employed to mount four separate transformers to a common base plate. Each transformer is fitted with appendages such as four cylindrical legs, each leg being shaped with a circular undercut of reduced cross-section adjacent the free end of the leg. The base plate is formed with sets of keyhole-shape or teardrop-shape holes, with each set of holes located to accommodate the legs of a given transformer. When all four transformers have been inserted and then slid into the latched position, a latch plate is fastened by one latch screw to the base plate. The latch plate is of a shape and size to abut against at least one leg of each transformer and to bias the undercut section of each transformer leg snugly against an edge of a base plate hole.

Abstract: A current rectifier is provided and generally comprises: a p-channel transistor and an n-channel transistor having common gates connected to ground and common sources connected to an input current I.sub.in ; and a first current mirror with its input connected to the drain of the n-channel transistor, and its output connected to the drain of the p-channel transistor. The current rectifier preferably also includes a second current mirror with the drain of the p-channel transistor as an input to the second current mirror and the rectified output current I.sub.out as an output of the second current mirror. If an offset to the rectified current is desired, a third current mirror having a bias or offset current as an input and the output of the second current mirror as an output may be included.

Abstract: Methods for establishing and maintaining synchronization between communicating multiplexers are provided, wherein a first multiplexer having a frame format multiplexes at least data according to the frame format, and wherein the second multiplexer demultiplexes at least said data according to the frame format, and synchronization is established by: providing the frame format with bit positions for a plurality of bits including first predetermined bit positions for a plurality of checksum bits, and second predetermined bit positions for bits other than checksum bits; calculating a checksum for the bit values of bits located at said second predetermined bit positions, and inserting bits representing the said calculated checksum into said first predetermined bit positions; sending bits including bits located at said first and second predetermined bit positions in said frame format from said first multiplexer to said second multiplexer; and establishing synchronization between said first and second multiplexers b

Abstract: Methods and apparatuses for efficiently allocating bandwidth to data, control and multiplexer overhead and for providing flexible data rates and control rates are provided. The apparatuses of the invention are used in a time division miltiplexer which multiplexes for transmission over and for receipt from at least one aggregate line in accord with at least one frame, data and control information from a plurality of channels and multiplexer overhead information.

Abstract: The invention is an enclosure for containing several printed circuit boards. Detechable brackets for mounting the enclosure to a rack, detachable latching door hinges and a combination of detachable members are assembled in an improved housing for detachably enclosing mounted printed circuit boards and other modular components and includes a base, a cover having a top and depending sides provided with slots; and vertical card guide brackets and a pivotable door. These detachable members are formed so as to to latch together into an integral assembly. The door when pivoted to the open position is held as a tray in the horizontal plane of the base and does not drop below the base, with a peripheral rim of the door serving as sides of the tray.

Abstract: A bit interleaved multiplexer system permitting byte synchronization of apparatuses communicating thereon without the consumption of additional aggregate bandwidth is provided. The system comprises a multiplexer, a demultiplexer, and an aggregate line. The multiplexer includes a transmit frame which includes a memory means and at least one recirculating counter which is programmed according to a framing algorithm, and a transmit data buffer and transmit mark buffer for each terminal which is to be connected to the system. Every time the transmit frame requests a predetermined bit of a byte (e.g. an MSB), a "1" is marked in the mark buffer. When a bit leaves the mark buffer it causes the terminal to write a bit into the transmit data buffer, with the written bit being an MSB when the bit leaving the mark buffer is a "1".

Abstract: A regenerative strobe circuit for a CMOS logic gate which only dissipates energy during the strobing of the inputs into the logic array is provided. The logic gate is connected between an output node and a first voltage source. The regenerative strobe circuit includes a first transistor (P channel) which is connected between a second voltage source and the output node, a complementary inverter having P channel transistor and N channel transistor, and second and third transistors which are respectively gate controlled by a strobe signal and a signal related to the strobe signal. The second transistor (P channel) is also connected between the second voltage source and the source of the P channel transistor of the complementary inverter. The third transistor (preferably P channel) is connected to the gate of the first transistor as well as to the source of the N channel transistor of the complementary inverter.

Abstract: An A-D converter for providing the general successive rectification algorithm V.sub.out =2.vertline.V.sub.in .vertline.-V.sub.ref is disclosed. One stage of a synchronous parallel converter generally comprises a comparator, and an op amp with V.sub.in as an input to its inverting input, the noninverting input connected to ground, and the output being V.sub.out, with a first capacitor bridging the inputs of the op amp, and a second capacitor of half the capacitance of the first capacitor feeding back from the output of the op amp to its noninverting input. The location and capacitance values of the first and second capacitors perform the amplification function. Switches between the first capacitor and the op amp provide rectification, while a third capacitor between V.sub.ref and the inverting input of the op amp provides the function of subtracting V.sub.ref. Stages are cascaded such that V.sub.out of one stage is the V.sub.in of the next stage. Each stage's V.sub.

Abstract: An apparatus for converting an input voltage into a related output current, is disclosed and generally comprises: a resistance means in series with the voltage input; first and second double output current mirrors, wherein each output of the first double output mirror is connected to a corresponding output of the second double output mirror, and the inputs of the double output current mirrors are connected; and an operational amplifier with the inverting input connected to ground, the noninverting input connected to the resistance means, and the op amp output connected to the inputs of the first and second double output mirrors, wherein first outputs of the first and second double output mirrors are connected to the noninverting input of the operational amplifier, and the second outputs of the first and second double output mirrors are connected to the output current.

Abstract: A continuous time domain parallel analog to digital converter is provided for accomplishing the general successive rectification algorithm I.sub.out =2.vertline.I.sub.in .vertline.-I.sub.ref. One stage of the continuous parallel converter comprises a complimentary transistor pair and three current mirrors. The transistor pair and a first current mirror and a second current mirror act as a rectifier. The complimentary transistor pair has I.sub.in connected to common sources, and common gates connected to ground. A first current mirror has its input connected to the drain of the n-type transistor of the complimentary pair and its output connected to the drain of the p-type transistor. The second current mirror acts as an amplifier by having its input transistors being half the width of the corresponding output transistors. The second mirror has its input connected to the output of the first current mirror, and its output going to I.sub.out. The third current mirror acts to subtract I.sub.

Abstract: A method and apparatus are described for automatically placing a modem in the answer or originate mode of operation without the use of a ring detector or a manually operated answer/originate mode selection switch. A timer and two latches are connected in the modem in such a fashion that when the modem is switched into operation it is in the originate mode. For a period of time determined by the timer, the modem looks for the receipt of an answer tone from a remotely located modem. If the answer tone is detected within this time, the modem remains in the originate mode and completes a handshaking sequence with the remote modem. If, however, the answer tone is not received, the modem automatically switches to the answer mode of operation and transmits an answer tone as part of the handshaking sequence.

Abstract: A method and apparatus are described for automatically generating the frame that is used in a bit-interleaved time division multiplexer (TDM). The apparatus comprises a microprocessor, two random access memories in which are stored the channel select signals, device for determining the transmission frequencies of each channel and a computer program which is stored in the memory of the computer for calculating the distribution of the channel select signals in the frame. With such a system, the frame can be reconfigured in about thirty seconds. Two random access memories are preferably used for the storage of the channel select signals. While the signals stored in one memory are being used to generate the actual frame, a new set of channel select signals can be stored in the other memory. After such an updated frame is written in the second memory, the task of generating the channel select signals can be switched from the first memory to the second memory without loss of any data from any of the data channels.

Abstract: A synchronization technique in which the frame used for synchronization is different from that used for normal data communiction and contains few if any bits other than those used to establish synchronization. At the beginning of data communication, the synchronization frame is stored in one of a pair of memories and this frame is read out of the memory onto a communication channel between the local and remote stations. At the same time, the other memory is used to store the frame that is normally used for data communication. When synchronization is established between the local and remote stations, signal generation shifts from the first memory to the second; and the second memory immediately begins to produce the channel select and overhead signals needed for data communication. Illustratively, the synchronization frame contains less than one hundred bits and in a preferred embodiment a total of forty-eight bits are used for synchronization.

Abstract: A method and apparatus are described in which the control signals for a data channel are transmitted along with the channel aaddress. The control signal and its address are transmitted on a bit interleaved basis in response to CONTROL select signals that are generated as part of the frame. In accordance with the invention, the CONTROL select signals are distributed relatively uniformly throughout the frame. At the receiver, the bits of the control signal and its address are reassembled and the address is used to route the control signal to its proper channel. Further, the bandwidth assigned to control signaling is increased by inserting CONTROL select signals in all time slots that are available in the frame after the necessary channel select signals and other overhead select signals have been assigned. This technique is particularly advantageous in a system having a fixed aggregate transmission bandwidth, variable loads and the capability of automatically reconfiguring the frame.

Abstract: A method and apparatus are described for ensuring that control signals from every data channel are transmitted periodically regardless of any change in these control signals. The apparatus comprises a counter for counting the number of control signals transmitted, decision logic for determining when it is time to transmit a set of control signals regardless of any change in these signals and circuitry for selecting the channel whose signals are to be transmitted. The apparatus provides additional equipment for determining when the control signals for a particular channel have changed and for transmitting such signals with suitable error checking. The apparatus also provides equipment for interleaving the two flows of control signals without loss of the control signals which are changed.

Abstract: A clock rate generator is described which can be programmed to provide an output clock rate that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter, a programmable memory, reset logic and a clocking control. A standard clock is applied to the counter so that the counter is advanced by one for each clock bit. The output of the counter is connected to the input lines of the programmable memory where a pattern of binary ones and zeros are stored. The output of the programmable memory is applied to the clocking control to combine successive bits of the same polarity. The divisor M is determined by the number of standard clock counts between successive resets of the counter. The multiplier N is determined by the number of output cycles from the clocking control between successive resets of the counter.

Abstract: A transistorized keying circuit is described which provides for both polar and neutral interfacing. The circuit comprises an oscillator, an AND gate, an exclusive OR gate, a transformer, and two similar output circuits each of which is connected to the secondary of the transformer. The oscillator produces a high frequency binary output signal having an asymmetric duty cycle. The output of the oscillator and a low frequency data signal are applied to the AND gate. The output of the AND gate and another low frequency data signal are applied to the exclusive OR gate whose output is amplified and applied to the primary of the transformer. Each output circuit coupled to the secondary of the transformer comprises a switching transistor for switching a supply voltage onto a transmission line and a peak detector for controlling the operation of the switching transistor.

Abstract: A method and apparatus are disclosed which provide a common handshaking protocol for the 201, 202 and 208 modems. In accordance with the invention, connection of answer modem and originate modem to the communication line is followed by a period of silence that is sufficiently long to reactivate any echo suppressors in the communication line. Thereafter at least two training sequences are transmitted, one from the originate modem to the answer modem and the other from the answer modem to the originiate modem, each training sequence being sufficiently long to train up any echo canceller in the line. The lengths of the training sequences as received are compared with their lengths as transmitted to determine if the length of the sequence was shortened by an echo suppressor. If the length of the training sequences as received are significantly shorter than their lengths as transmitted, a sacrificial carrier is transmitted at the beginning of each transmission of data in a new direction.

Abstract: Portions of an adaptive equalizer can be used for exact preamble synchronization by modifying the digital filter section to recognize pre-determined sequences of signals in the received signal. This may be accomplished by applying to the modifying means of the digital filter input signals which are proportional to the complex conjugate of the signals in the received signal. When the signals in the tapped delay line are aligned with this complex conjugate, the output of the summing means will be discernibly greater than otherwise. As a result, a threshold device can be used to recognize the exact baud time the preselected signals in the received signal are contained in the tapped delay line.

Abstract: A method and apparatus are described for generating a sequence of signals using first and second read-only memories, a counter associated with each memory as an address register, a source of timing signals connected to the input of each counter, decoding apparatus for the output of each memory and control logic to enable only one memory at a time. The two memories are organized in hierarchical fashion so that the first memory controls the second. Advantageously, the first memory provides for generation of unique portions of the sequence while the second memory provides for generation of repeated portions of the sequence.