Abstract: A decision feedback equalizer is configured to equalize an input signal to generate a recovered output signal. Linear feed-forward filter circuitry is configured to provide a linearly filtered output signal based on the input signal. Composite trellis decoder circuitry configured to process a combined signal that is based on a combination of at least the linearly feed-forward filtered output signal and on output of linear or non-linear feedback filter circuitry, in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal, to provide a trellis-decoded output signal as input to the linear or non-linear feedback filter circuitry. The composite trellis decoder circuitry is further configured to provide a particular phase output of the combined signal, based on the state metrics, as the decoded output signal.

Abstract: A method of automatic gain control in both analog and digital domain is performed by receiving an incoming analog signal, determining an overall gain factor, determining a coarse analog gain control value and a fine digital gain control value, each of which, when taken together substantially equals the already determined overall gain factor, modifying the incoming analog signal using the coarse analog gain control value to form a coarsely adjusted digital signal, digitizing the coarsely adjusted digital signal, and using the fine digital gain control value to process the coarsely adjusted digital signal to form an outgoing digital signal, wherein the outgoing digital signal has been modified in both the analog domain and subsequently in the digital domain to achieve an appropriate signal to noise ratio.

Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. A group of transfer parameters as queue entries allow code and data for an algorithm to be transferred between both local and external memory.

Abstract: Keys (e.g., decryption key, authentication key) are stored in a non-volatile memory of a display unit. The keys are retrieved in encrypted form into an integrated circuit. The integrated circuit decrypts the keys and uses the keys. As the keys are available in decrypted form only within the integrated circuit and potentially only during use, the keys may not be available to unauthorized third parties.

Abstract: A method and apparatus for displaying different presentations of program material allows various presentations of a DVD movie, for example, to be displayed on a display for a user's selection. The various presentations might involve different angles from which a user must select or different chapters from which a program should begin. The selection of a presentation is facilitated by displaying the various options on a single display such that the user can quickly choose which presentation to choose. Furthermore, audio is provided with chapter presentations to assist a user in selecting a chapter from where playback should be initiated.

Abstract: A computing system comprising a host device which includes a serial communication bus and a processor for controlling communication over the serial communication bus. The computing system further comprises one or more peripheral devices connected to the communication bus. Communication between the host device and the peripheral devices is facilitated by a communication protocol, which includes a procedure for discovering whether the configuration of peripheral devices connected to the communication bus has changed. The discovery procedure starts by the host device sending a first command to all peripheral devices connected to the serial communication bus to determine if the configuration of any of the peripheral devices has changed. If a new peripheral device has been added to the communication bus, the host sends a focus command to a first comm bus port on the communication bus to focus that particular port.

Abstract: A method and an apparatus for performing the method of decoding and playing in reverse MPEG encoded content. The MPEG encoded content comprises a plurality of pictures frames. The picture frames are comprised of one or more picture frame types selected from the group of picture frame types including I-frames, P-frames, and B-frames. The method and the apparatus for performing the method comprise the steps of obtaining a group of MPEG picture frames (“GOP”), determining the total number of picture frames in the GOP, and setting an index value equal to the total number of picture frames in the GOP. Next, a picture frame F that has a display order equal to the index value is decoded and displayed, and the earliest B-frame that depends upon frame F is determined. All the B-frames that depend upon frame F are decoded and displayed from highest display order to lowest display order, and the index value then is set to a value equal to one less than the display order of the earliest B-frame that depends upon frame F.

Abstract: A transmission efficient packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed. The transmission efficient interface includes a bi-directional auxiliary channel arranged to transfer information between the multimedia source device and the multimedia sink device and vice versa, wherein the information transferred over the auxiliary channel includes a set of packet attributes. The interface also includes a unidirectional main link arranged to carry a number multimedia data packets from the transmitter unit to the receiver unit each having a multimedia data packet header. In the described embodiment, each of the headers is substantially reduced in size over what would otherwise be necessary since the packet attributes are communicated via the auxiliary channel prior to the transmission of the main link packets over main link thereby minimizing the packet overhead and providing a very high main link efficiency.

Abstract: A video display system is disclosed. The video display system comprises a display generator for providing a display timing signal and a frame rate converter for receiving input video data, input video timing, and for providing output video data. The system includes a control logic for receiving a frame rate indication signal, the video input timing and the display timing signal. The control logic changes the display frame rate of the display generator in accordance with the native frame rate of the program, and in such a way as to maintain a stable image throughout.

Abstract: An apparatus and method for allowing color adjustments in display devices is disclosed The apparatus comprises a multi-resolution structure for providing color adjustments; and an interpolator for interpolating at least one offset of the multi-resolution structure. An apparatus and method in accordance with the present invention uses a combination of color look-up tables with different levels of resolution, followed by interpolation to provide a display process which has high resolution but utilizes minimal memory. In so doing, memory is used for high-resolution areas only where needed. The multi-resolution structure is a very good approximation to the theoretical mapping table in the areas where it is needed. At the same time, since the high resolution areas are localized, a significant reduction in memory storage is possible.

Abstract: A method for receiving OSD data over from a computer for display on a monitor over a transmission link that includes, launching an OSD application on the computer; receiving an OSD control command at the computer; encoding the OSD control command by the OSD application; converting the encoded OSD control command into an OSD data packet; converting the OSD data packet into at least two OSD pixel patterns, sending the two OSD pixel patterns over the transmission link to the monitor, and displaying the OSD.

Abstract: A method, system and apparatus for color management that directly acts upon the hue, saturation, and luminance value of a pixel instead of its U and V value. Additionally, instead of dividing the color space into uniform areas, the color space is divided into multiple user-defined regions. The detection of a pixel is based on its hue, saturation, and luminance value, so a single set of values can define the correction for an entire hue.

Abstract: An all-digital frequency conversion apparatus is provided that achieves frequency conversion using a simple phase detector and integer and fractional phase feedback information from a digital oscillator output. In an embodiment, a target phase accumulator unit generates a target phase signal to the phase detector unit. The target phase accumulator unit receives inputs from a reference signal input, and a target phase input value. The digital phase detector unit receives the reference signal, a current phase feedback input signal, and the target phase input signal. The phase detector unit outputs a frequency setting signal to a frequency value generator unit. The detector output is based on the difference between the current phase and the target phase. A frequency value generator unit is configured to output a frequency value signal to a digital oscillator unit that generates a corresponding digital output signal that is directly fed back to the current phase feedback input of the phase detector unit.

Abstract: In a system having a bi-directional auxiliary channel arranged to transfer information between a video source and a video display and vice versa and a unidirectional main link arranged to carry a number multimedia data packets from the video source to the video display, a method of establishing a stable main link. The method is carried out by performing a link training session carried out over the auxiliary channel to establish the stable main link, prior to starting transmission of multimedia data packet streams from a video transmitter to a video receiver over the main channel.

Abstract: A general method is provided to achieve frequency conversion in an all-digital frequency conversion device that produces an output signal having a selectable phase and frequency that is substantially synchronous with the input signal to be converted. A multiplicity of time-shifted signals is generated, and appropriate ones are selected to set and reset an output signal. An apparatus, computing system, and software product that implement the present invention are also provided.

Abstract: A transmission efficient packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed. The transmission efficient interface includes a bi-directional auxiliary channel arranged to transfer information between the multimedia source device and the multimedia sink device and vice versa, wherein the information transferred over the auxiliary channel includes a set of packet attributes. The interface also includes a unidirectional main link arranged to carry a number multimedia data packets from the transmitter unit to the receiver unit each having a multimedia data packet header. In the described embodiment, each of the headers is substantially reduced in size over what would otherwise be necessary since the packet attributes are communicated via the auxiliary channel prior to the transmission of the main link packets over main link thereby minimizing the packet overhead and providing a very high main link efficiency.

Abstract: A method and apparatus that allows a display device to adaptively and automatically control display contrast and color is disclosed. The method and system in accordance with the present invention can be described by the following sequential process: 1. Separating an input image data value into its luma and chroma components. 2. Collecting the luma distribution data over the entire image or a specified window. 3. Analyzing the luma distribution. 4. Generating an appropriate contrast control response that modifies the input luma component to generate an output luma component, on a pixel by pixel basis. 5. Analyzing the input luma component and the output luma component, and an input chroma component, to generate an appropriate modification for the chroma component, on a pixel by pixel basis.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for reducing the power consumption of a microprocessor. One or more signal transitions in an instruction set of a microprocessor are profiled. A probability of occurrence is assigned to each instruction in the instruction set. A binary operation code is assigned to each instruction, based on the probability of occurrence for the instruction. The instructions having the highest probability of occurrence are assigned operation codes that require fewer signal transitions. As a result, the power consumption of the microprocessor is reduced.

Abstract: Detecting when the on-board power supply is powered on or off by an auto activity detection circuit by determining if the reference clock signal (TCLK) is toggling and if the reference clock signal is toggling, then charging a capacitor to a high voltage in the auto activity detection circuit based on the toggling reference clock signal, and outputting an on-board power supply activity signal based upon the high voltage by the auto activity detection circuit indicative of whether or not the on-board power supply is active

Abstract: A video controller having a processor for processing executable instructions and associated data and a number of data ports, a method of acquiring extended display identification data (EDID) by a requesting one of the data ports is described. When on-board power supply is activated, an off-board power supply is deactivated and then the now active on-board power supply provides power to a memory device used to store the EDID and the executable instructions and associated data and to an on-board clock circuit capable of providing a high frequency clock signal. The on-board clock circuit, in turn, provides the high frequency clock signal from the on-board clock circuit to the memory device and if a memory read operation had been in progress when the on-board power supply was activated, then the memory read operation is completed.