Abstract: An apparatus and method for allowing color adjustments in display devices is disclosed The apparatus comprises a multi-resolution structure for providing color adjustments; and an interpolator for interpolating at least one offset of the multi-resolution structure. An apparatus and method in accordance with the present invention uses a combination of color look-up tables with different levels of resolution, followed by interpolation to provide a display process which has high resolution but utilizes minimal memory. In so doing, memory is used for high-resolution areas only where needed. The multi-resolution structure is a very good approximation to the theoretical mapping table in the areas where it is needed. At the same time, since the high resolution areas are localized, a significant reduction in memory storage is possible.

Abstract: A method for receiving OSD data over from a computer for display on a monitor over a transmission link that includes, launching an OSD application on the computer; receiving an OSD control command at the computer; encoding the OSD control command by the OSD application; converting the encoded OSD control command into an OSD data packet; converting the OSD data packet into at least two OSD pixel patterns, sending the two OSD pixel patterns over the transmission link to the monitor, and displaying the OSD.

Abstract: A method, system and apparatus for color management that directly acts upon the hue, saturation, and luminance value of a pixel instead of its U and V value. Additionally, instead of dividing the color space into uniform areas, the color space is divided into multiple user-defined regions. The detection of a pixel is based on its hue, saturation, and luminance value, so a single set of values can define the correction for an entire hue.

Abstract: An all-digital frequency conversion apparatus is provided that achieves frequency conversion using a simple phase detector and integer and fractional phase feedback information from a digital oscillator output. In an embodiment, a target phase accumulator unit generates a target phase signal to the phase detector unit. The target phase accumulator unit receives inputs from a reference signal input, and a target phase input value. The digital phase detector unit receives the reference signal, a current phase feedback input signal, and the target phase input signal. The phase detector unit outputs a frequency setting signal to a frequency value generator unit. The detector output is based on the difference between the current phase and the target phase. A frequency value generator unit is configured to output a frequency value signal to a digital oscillator unit that generates a corresponding digital output signal that is directly fed back to the current phase feedback input of the phase detector unit.

Abstract: In a system having a bi-directional auxiliary channel arranged to transfer information between a video source and a video display and vice versa and a unidirectional main link arranged to carry a number multimedia data packets from the video source to the video display, a method of establishing a stable main link. The method is carried out by performing a link training session carried out over the auxiliary channel to establish the stable main link, prior to starting transmission of multimedia data packet streams from a video transmitter to a video receiver over the main channel.

Abstract: A general method is provided to achieve frequency conversion in an all-digital frequency conversion device that produces an output signal having a selectable phase and frequency that is substantially synchronous with the input signal to be converted. A multiplicity of time-shifted signals is generated, and appropriate ones are selected to set and reset an output signal. An apparatus, computing system, and software product that implement the present invention are also provided.

Abstract: A transmission efficient packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed. The transmission efficient interface includes a bi-directional auxiliary channel arranged to transfer information between the multimedia source device and the multimedia sink device and vice versa, wherein the information transferred over the auxiliary channel includes a set of packet attributes. The interface also includes a unidirectional main link arranged to carry a number multimedia data packets from the transmitter unit to the receiver unit each having a multimedia data packet header. In the described embodiment, each of the headers is substantially reduced in size over what would otherwise be necessary since the packet attributes are communicated via the auxiliary channel prior to the transmission of the main link packets over main link thereby minimizing the packet overhead and providing a very high main link efficiency.

Abstract: A method and apparatus that allows a display device to adaptively and automatically control display contrast and color is disclosed. The method and system in accordance with the present invention can be described by the following sequential process: 1. Separating an input image data value into its luma and chroma components. 2. Collecting the luma distribution data over the entire image or a specified window. 3. Analyzing the luma distribution. 4. Generating an appropriate contrast control response that modifies the input luma component to generate an output luma component, on a pixel by pixel basis. 5. Analyzing the input luma component and the output luma component, and an input chroma component, to generate an appropriate modification for the chroma component, on a pixel by pixel basis.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for reducing the power consumption of a microprocessor. One or more signal transitions in an instruction set of a microprocessor are profiled. A probability of occurrence is assigned to each instruction in the instruction set. A binary operation code is assigned to each instruction, based on the probability of occurrence for the instruction. The instructions having the highest probability of occurrence are assigned operation codes that require fewer signal transitions. As a result, the power consumption of the microprocessor is reduced.

Abstract: Detecting when the on-board power supply is powered on or off by an auto activity detection circuit by determining if the reference clock signal (TCLK) is toggling and if the reference clock signal is toggling, then charging a capacitor to a high voltage in the auto activity detection circuit based on the toggling reference clock signal, and outputting an on-board power supply activity signal based upon the high voltage by the auto activity detection circuit indicative of whether or not the on-board power supply is active

Abstract: A method of automatic gain control in both analog and digital domain is performed by receiving an incoming analog signal, determining an overall gain factor, determining a coarse analog gain control value and a fine digital gain control value, each of which, when taken together substantially equals the already determined overall gain factor, modifying the incoming analog signal using the coarse analog gain control value to form a coarsely adjusted digital signal, digitizing the coarsely adjusted digital signal, and using the fine digital gain control value to process the coarsely adjusted digital signal to form an outgoing digital signal, wherein the outgoing digital signal has been modified in both the analog domain and subsequently in the digital domain to achieve an appropriate signal to noise ratio.

Abstract: In digital display circuitry, configured to display an image encoded in an analog display signal, the digital display circuitry includes analog-to-digital converter (ADC) circuitry to recover pixel data elements of the image. During vertical blanking intervals of the analog display signal, the ADC circuitry is calibrated. Outside the vertical blanking intervals, the ADC circuitry is used to convert information in the analog display signal into digital representations of the pixel data elements. For example, the calibrating may include determining more acceptable values for certain ones of the operational parameters of the ADC circuitry.

Abstract: A method, system and apparatus for synchronizing an analog video signal to an LCD monitor is described. For each of a succession of associated video frames are surveyed for a number of displayed features based upon a pseudo-random selection of regions into which the displayed video frame is divided. During successive associated video frames, a minimum number of features each is which is generated by an associated pixel clock is determined based upon a pre-selected number of scans. Subsequent to the determination of the minimum number of features, a transition region for each of plurality of horizontal resolution values is determined by scanning through a selected number of pixel clock phases. Based upon a minimum transition zone corresponding to a maximum change in the number of features for a particular pixel clock phase, an associated horizontal resolution is provided.

Abstract: Automatically and adaptively controlling contrast and color of a display device by computing a normalized histogram of a current image, computing degrees of correlation between the normalized histogram and a number of template histograms, sorting the template histograms based upon the associated degrees of correlation, selecting a number of the best correlated template histograms based on the sorting, blending the selected the transfer functions associated with the selected template histograms to form a blended transfer function, and applying the blended transfer function to the current image.

Abstract: Managing power in a display controller having an on-board power supply coupled to a host device having an off-board power supply by way of a connector is described. If the on-board power supply is active, then power is supplied to the display controller by the off-board power supply by way of the connector and a low frequency clock arranged to provide a low frequency clock signal is turned on. Alternatively, when it is determined that the on-board power supply is active, then power is supplied to the display controller by the on-board power supply only, the low frequency clock is turned off and a high frequency clock arranged to provide a high frequency clock signal is turned on.

Abstract: In a VESA standard compliant display controller having a processor arranged to process executable instructions and associated data, a memory device arranged to store EDID and the executable instructions and associated data, a number of data ports coupled to the memory device by way of an 12C data bus each coupled to a host device, a method of transferring EDID from the memory device over the 12C data bus to a requesting one of the data ports while servicing a processor memory access request without clock stretching.

Abstract: A display controller includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device that is always available for access by the data ports and/or the processor regardless of a power state of the display controller, a data buffer for storing EDID read from the memory device, and an arbitration circuit for arbitrating memory device access requests between the processor and a requesting data port wherein when the data buffer is not almost empty, then the arbitration circuit grants the processor access to the memory wherein when the data buffer is almost empty, then the arbitration circuit grants only the requesting data port access to them memory so as to replenish the data buffer with read EDID.

Abstract: A transmission efficient packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed. The transmission efficient interface includes a bi-directional auxiliary channel arranged to transfer information between the multimedia source device and the multimedia sink device and vice versa, wherein the information transferred over the auxiliary channel includes a set of packet attributes. The interface also includes a unidirectional main link arranged to carry a number multimedia data packets from the transmitter unit to the receiver unit each having a multimedia data packet header. In the described embodiment, each of the headers is substantially reduced in size over what would otherwise be necessary since the packet attributes are communicated via the auxiliary channel prior to the transmission of the main link packets over main link thereby minimizing the packet overhead and providing a very high main link efficiency.

Abstract: A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.

Abstract: A video controller having a processor for processing executable instructions and associated data and a number of data ports, a method of acquiring extended display identification data (EDID) by a requesting one of the data ports is described. When on-board power supply is activated, an off-board power supply is deactivated and then the now active on-board power supply provides power to a memory device used to store the EDID and the executable instructions and associated data and to an on-board clock circuit capable of providing a high frequency clock signal. The on-board clock circuit, in turn, provides the high frequency clock signal from the on-board clock circuit to the memory device and if a memory read operation had been in progress when the on-board power supply was activated, then the memory read operation is completed.