Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. The system can support the interaction of multiple independent programs in external memory.

Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. The system can support the interaction of multiple independent programs in external memory.

Abstract: A method and system for scaling an image in accordance with the present invention is disclosed. The method utilizes a plurality of interpolators operating in parallel. Each interpolator operates with a different spatial offset with respect to the other. The final output is the average the output of each interpolator. Normally the initial value of the horizontal and vertical DDA's is zero. Offset is introduced by introducing an initial value in the DDA. Offset has the physical effect of manipulating the weights required for the averaging process in interpolation. Horizontal offset is the initial value in the Horizontal DDA while the vertical offset is the initial value in the Vertical DDA. The present invention relates to implementation in a semiconductor integrated circuit but the concepts can be used in software based image resizing (scaling) algorithms too.

Abstract: In accordance with the invention, a multi-processing unit system including a plurality of processing units in direct communication via a communication bus is presented. The system includes a communication bus arbiter having a communication packet multiplexer. Each of the processing units include a communication bus interface comprising a transmitter interface and a receiver interface. Each of the transmitter interfaces are connected to the communication packet multiplexer of the communication bus arbiter via separate 32-bit interfaces. Each of the receiver interfaces is connected to the communication packet multiplexer of the communication bus arbiter via a single 32-bit bus. The system may further comprise a first control signal connection means for communicating control signals between the transmitter interface and the communication bus arbiter and a second control signal connection means for communicating control signal between the receiver interface and the communication bus arbiter.

Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. A group of transfer parameters as queue entries allow code and data for an algorithm to be transferred between both local and external memory.

Abstract: A method, system and apparatus for detecting a sub-pixel pair susceptible of producing a flicker event in an image from a video signal source displayed on a liquid crystal display (LCD) unit is described. A two dimensional flicker pattern analysis is performed on a selected group of sub-pixels some of which are included in a first plurality of sub-pixels that includes a first current sub-pixel and a first next sub-pixel included in a first video frameline and a remainder of which are included in a second plurality of sub-pixels included in a second video frameline that is received, in real time, from the video signal source that includes a second current sub-pixel and a second current sub-pixel.

Abstract: A system for processing information, such as audio/video information utilized in a DVD player, can be implemented without the need for a buffer, such as a track buffer, located between the source of audio/video information and the demultiplexer which parses a packet of data. The packet of data can then be parsed into audio, video, subpicture, or navigation, portions and stored for decoding. In one embodiment, a DVD player utilizes a circuit that is synchronized to the speed of the DVD drive rather than to the speed of the decoders for each portion of data.

Abstract: A computing system comprising a host device which includes a serial communication bus and a processor for controlling communication over the serial communication bus. The computing system further comprises one or more peripheral devices connected to the communication bus. Communication between the host device and the peripheral devices is facilitated by a communication protocol, which includes a procedure for discovering whether the configuration of peripheral devices connected to the communication bus has changed. The discovery procedure starts by the host device sending a first command to all peripheral devices connected to the serial communication bus to determine if the configuration of any of the peripheral devices has changed. If a new peripheral device has been added to the communication bus, the host sends a focus command to a first comm bus port on the communication bus to focus that particular port.

Abstract: A self-adaptive method for controlling a self-biased PLL system is disclosed. The method comprises providing an application-dependent input frequency; and providing an application-dependent number N representing the ratio between the output frequency and the application-dependent input frequency to the PLL system. In a system and method in accordance with the present invention, the bandwidth and damping factor are tracked, not only with the input frequency but with the divider ratio as well. Therefore, jitter is minimized for any operating condition (i.e., input frequency variations [N]). The charge-pump current is made to be proportional to the VCO current ID and inversely proportional to the frequency range N; and the loop filter resistor is made to be inversely proportional to the square root of the VCO current ID and proportional to N. In so doing, the bandwidth and damping factors can be tracked more comprehensively.

Abstract: A method and apparatus used to step and correct the position of raster lines in a sinusoidal or zig-zag deflection system. By combining the magnetic flux generated with a rotation “twister” coil and a vertical deflection coil, scan lines can be uniformly spaced and separated nearly to their ends. Accordingly, the magnetic flux generated with the twister coil is adjusted going in the left to right direction then reversed in polarity and readjusted while returning from right to left. It is this controlled twister flux that combines with the linear vertical deflection flux to straighten and then step each scan line to produce an aligned raster.

Abstract: A method and apparatus are provided whereby the motion between two video fields of opposite parity may be measured so as to discriminate between the presence of motion and lack thereof. The level of motion at a specified position is determined by comparing a first motion value derived from successive fields of opposite parity with a second motion value derived from successive fields of the same parity at the spatial location corresponding to that used to generate the first motion value. This determination is made with one field being common to the first and second motion values, and taking the minimum of the first and second motion values to be the motion value at that position.

Abstract: A method for measuring motion at a horizontal and vertical position between video fields of opposite parity comprising the steps of measuring the signal values of at least two vertically adjacent pixels from a video field of one parity and at least two vertically adjacent pixels from a video field of the opposite parity such that when taken together, the pixels represent contiguous samples of an image at said horizontal and vertical position, and determining whether the signal value of any of the pixels lies between the signal values of adjacent pixels in the field of opposite parity and in response outputting a zero motion value, otherwise, outputting a motion value equal to the lowest absolute difference between any of the pixels and its closest adjacent pixel in the field of opposite parity.

Abstract: A general method is provided to achieve frequency conversion in an all-digital frequency conversion device that produces an output signal having a selectable phase and frequency that is substantially synchronous with the input signal to be converted. A multiplicity of time-shifted signals is generated, and appropriate ones are selected to set and reset an output signal. An apparatus, computing system, and software product that implement the present invention are also provided.

Abstract: An all-digital frequency conversion apparatus is provided that achieves frequency conversion using a simple phase detector and integer and fractional phase feedback information from a digital oscillator output. In an embodiment, a target phase accumulator unit generates a target phase signal to the phase detector unit. The target phase accumulator unit receives inputs from a reference signal input, and a target phase input value. The digital phase detector unit receives the reference signal, a current phase feedback input signal, and the target phase input signal. The phase detector unit outputs a frequency setting signal to a frequency value generator unit. The detector output is based on the difference between the current phase and the target phase. A frequency value generator unit is configured to output a frequency value signal to a digital oscillator unit that generates a corresponding digital output signal that is directly fed back to the current phase feedback input of the phase detector unit.

Abstract: A method and apparatus for reducing the appearance of moiré in a digitally resized image wherein each input pixel value is mapped to a new value by means of a first correction function prior to being resized. At the output of the resizing engine, each pixel in the resized image is mapped to a further new value by means of a second correction function prior to being displayed. The second correction function is chosen such that the intensity of light output from the display device is substantially proportional to the value of the signal from the resizing engine, taking into account the combined transfer functions of the second correction means and the physical display device (i.e. the second correction function is substantially the inverse of the display transfer characteristic).

Abstract: A programmable delay element is provided for delaying a digital input signal. The programmable delay element comprises a discharge capacitor adapted to be precharged to a predetermined voltage in response to a first transition of the digital input signal. A transistor switch of a first type is provided for precharging the discharge capacitor to a predetermined voltage. A discharge current source is connected via a sense node to the discharge capacitor for discharging the capacitor in response to a subsequent opposite transition of the digital input signal. A transistor switch of a second type is provided for connecting the discharge capacitor to the discharge current source and thereby discharging the discharge capacitor. A reference voltage source is provided for applying a reference voltage to a reference node.

Abstract: A method of de-interlacing used to convert an interlaced video signal to a progressively scanned format utilizing vertical temporal filtering to generate the missing lines, utilizing appropriate filter coefficients to give a desired vertical frequency response, and filter utilizing coefficients such that the total combined contribution from all fields is unity while the total contribution from each individual field is chosen so as to boost higher temporal frequencies which has the perceived effect of increasing the sharpness of moving edges. Furthermore, in order to avoid certain unwanted artifacts, the lines of the current field are modified using a vertical temporal filter with similar temporal boosting properties to that which was used to generate the missing lines.

Abstract: A method of generating an upsampled target pixel positioned between two lines of input source data includes the step of comparing pixels of different lines of the source data in a region surrounding the upsampled target pixel to be generated in at least two different directions. An interpolation direction based on the comparison is selected and interpolations between selected pixels of the source data in the determined interpolation direction are carried out to compute intermediate pixels on a line segment passing through the upsampled target pixel. An interpolation between the intermediate pixels is carried out to generate the upsampled target pixel. An apparatus for performing the method is also disclosed.

Abstract: A method and apparatus are provided for converting interlaced video fields of arbitrary size to progressive scan format video frames of arbitrary size. The method and apparatus of the invention provide consistent conversion quality even while output video dimensions are scaled in real-time. According to a first aspect of the invention the space between output lines is calculated with respect to the input fields. According to a second aspect, the output line spacing information is used to calculate the final line positions in a progressive scan output frame.

Abstract: A method of generating an upsampled target pixel positioned between two lines of input source data includes the step of comparing pixels of different lines of the source data in a region surrounding the upsampled target pixel to be generated in at least two different directions. An interpolation direction based on the comparison is selected and interpolations between selected pixels of the source data in the determined interpolation direction are carried out to compute intermediate pixels on a line segment passing through the upsampled target pixel. An interpolation between the intermediate pixels is carried out to generate the upsampled target pixel. An apparatus for performing the method is also disclosed.